BB80 Prototype, Bare Bones Z80, A Simple Z80 SBC

Introduction

BB80 prototype explores the concept of bare bones Z80 computer. The design is consisted of Z80, RAM, and 22V10.

Features

Z80 at 25MHz
64K RAM
GAL22V10 as bootstrap and serial port
Bit-bang serial port, 15200 baud N82

Theory of Operation

22V10 has 10 outputs; eight of them have large sum-of-product array with 10 to 16 product terms per output. The number of product terms are not the same with pins 17, 18 having 16 product terms while pin 15,22 having 10 product terms. By selectively assigning the most used data bits to output with largest product terms and least used data bits to outputs with smaller product terms, a decent size ROM can be created out of 22V10's logic array. The size of ROM is data dependent and data bit pin assignment. By trials and errors, 40-50 bytes of Z80 program can be embedded in 22V10's logic array.

The 10 outputs of a 22V10 can be partition into 8 outputs for 40-50 bytes of ROM, and 2 outputs for RAM page register and register for serial transmitter. The RAM page register is cleared after reset so ROM occupies the entire memory space for read operations. However, RAM is still enabled and can accept data for write operations Another word, ROM is ready-only and RAM is write-only when RAM page register is cleared. RAM page register can be set by accessing IO space address 0x38. As soon as RAM page register is set, ROM becomes inactive and RAM occupies all 64K memory for read and write operations. The function of the ROM is to receive data from serial port and write to RAM while the page register is cleared. The program is such that when page register is set, Z80 continue execute in RAM the program that was previously loaded by ROM.

The serial port as implemented in 22V10 is a simple bit-bang serial transmitter and receiver. The serial receiver is a 4.7K resistor between serial receive terminal and Z80's data bit 7; while the serial transmitter is a writable register in I/O space 0x9E. Accessing IO address 0x9E causes the transmitter output to go low while accessing any other IO addresses cause the transmitter output to go high.

The ROM program in 22V10 is executed immediately after reset. It continuously samples data bit 7 (serial receive) for start bit; once start bit is detected, it waits 1-1/2 bit time to read in serial data and afterward sample serial data every bit time to a byte of data and write it into RAM starting from the address immediately after the IO instruction that set the RAM page register. There is no explicit jump instruction at the end of ROM program loading because as soon as the RAM page register is set, the program execution continue in RAM with code that was loaded by ROM.

The bootstrap ROM code is included below. It is 35 bytes long and fit easily in 22V10's sum-of-products arrays. The program ends at 0x22 when RAM page register is set, so location 0x23 is the beginning of an Intel file loader that loads and runs an application program.

                   0000009F  A        6 SerRx    equ 9fh        ;Read I/O with causing TX negate (high voltage level)
                   0000009E  A        7 SerTx    equ 9eh        ;access cause TX assert (low voltage level)
                   00000038  A        8 Page    equ 38h        ;Pageable ROM register
                             A        9             ;  cleared at reset, set to page out ROM
                   00000016  A       10 bit1_5    equ 22        ;constant for 1-1/2 bit time
                   0000000D  A       11 bit1    equ 13        ;constant for 1 bit time
                             A       12     org 0
00000000 0E 9F               A       13     ld c,SerRx    ;regC points to Serial receive
00000002 21 23 00            A       14     ld hl,progStart    ;HL points to memory for serial upload
00000005                     A       15 startBit:
00000005 ED 78               A       16     in a,(c)        ;(12)
00000007 FA 05 00            A       17     jp m,startBit    ;(10)
0000000A 1E 09               A       18     ld e,9        ;(7) 8 bit data + stop bit
0000000C 06 16               A       19     ld b,bit1_5    ;(7)
0000000E                     A       20 bitTime:
                             A       21 ;bit1_5 is 12+10+7+7+13(b-1)+8+12=328, or 13(b-1)=272, RegB=22
                             A       22 ;bit1 is 12+8+8+7+4+12+13(b-1)+8=218, or 13(b-1)=159, RegB=13
0000000E 10 FE               A       23     djnz bitTime    ;(13/8 for b=0)
00000010 ED 78               A       24     in a,(c)        ;(12)
00000012 CB 17               A       25     rl a        ;(8) put received data in carry
00000014 CB 1A               A       26     rr d        ;(8)
00000016 06 0D               A       27     ld b,bit1        ;(7)
00000018 1D                  A       28     dec e        ;(4)
00000019 20 F3               A       29     jr nz,bitTime    ;(12 taken/7 fall through)
                             A       30 ;when exit regD + carry flag contains the received data
                             A       31 ;  D[7] of regD is stop bit, carry flag is the least significant bit of the received data
0000001B CB 12               A       32     rl d        ;regD now contains the received data
0000001D 72                  A       33     ld (hl),d
0000001E 2C                  A       34     inc l        ;point to next RAM location, up to page boundary
0000001F 20 E4               A       35     jr nz,startBit
00000021 D3 38               A       36     out (Page),a    ;page out ROM
                             A       37 ;program is executing in RAM now
                             A       38 ;expect program to be loaded here by the bootstrap program.
00000023                     A       39 progStart: