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Table of Contents
VGARC, Text-based VGA Adapter for RC2014
Introduction
VGARC, rev1 replaces the previous exploratory rev0.1 and prototype designs. VGA rev1 is based on 4K of dual-port RAM shared between RC2014 bus and on-board video display circuitry. The 4K dual-port RAM issplitted into 1K of font tables and 3K of text memory. Both font tables and text memory can be accessed at any time without causing display flickering.
Features
8K bytes of dual port RAM to simplify communication between Z80 and video display logic
State machine in Altera EPM7128S CPLD generates the video timings
8×8 pixel font
Font lookup table resides in the dual port RAM and is user programmable
Display 56 lines, 80 characters per line
Theory of Operation
Design Information
Schematic
Gerber photoplots
CPLD design file
