Memory Map of VGA65 rev0

RAM $0-$EFFF. $0-$3FFF are common RAM; there are two banks of RAM from $4000 to $EFFF controlled by bank register. D[0] of bank register selects the banks. Bank register is cleared on reset.

Only Addresses A[0-5], A[12-15] are decoded so there are many aliase for I/O and ROM.

ROM is located at $FX_xx1x_xxxx. Locations are aliased multiple times, recommended addresses are $FFE0-$FFFF.

Bank reg is located at $FX_xx01_0010. Recommended address is $FF12. D[0] selects the banks; Bank register is cleared on reset. D[1]-D[7] are don't care bits.

PS2CLK control register is located at $FX_xx01_0100. Recommended address is $FF14. D[0] controls the PS2CLK output. Writing '1' to PS2CLK reg causes PS2CLK output to float allowing an external pull up resistor to pull it high. Writing '0' to PS2CLK reg causes PS2CLK output to go low. PS2CLK register is preset to 1 at reset thus its output is floating. Writing to D[1]-D[7] have no effects

PS2Data line is clocked in with the falling edge of PS2CLK. Reading PS2CLK control register at $FF14 display the value of PS2Data at D[7] and the value of PS2CLK at D[6].

Pixel shifter snoops data in addresses $4000-$EFFF; another word, accessing addresses in the range of $4000-$EFFF will load the data bus value into pixel shifter. This is the mechanism to load graphic data located in $4000-$EFFF and shift them out to video display.

SerData is located at $FX_xx01_1001. Recommended address is $FF19, bit-bang transmit
SerStat is located at $FX_xx01_1000. Recommended address is $FF18, read bit-bang serial receive in D[7] as well as last line of horizontal line.

CF interface is located at $FX_xx00_xxxx. Recommended address is $F000-$F007.