Engineering Changes for rev0 65ALL PC Board

Rev0 of 65ALL pc board has a significant numbers of engineering changes. The following is NOT a detailed description of each changes, but an overview of changes. This is to assist with design of next revision of pc board as well as understanding of changes to rev0 pc board.

There are changes in three general areas:

DPR is read-only on the video side and write-only on the 6502 side

• Permanently enable the video side of dual port RAM. Cut chip_enable_left (pin1) of DPR and ground it.
• Disable output enable of 6502 side of dual port RAM. Cut output_enable_right (pin 46) of DPR and tie it to VCC
• Reroute 4 addresses to 6502 side of the dual port RAM. Cut 6502's A12-A15 to DPR pin 38-41 and connect 6502's A4-A7 instead.

• Permanently enable RAM for fast access. Cut clock to chip_select of RAM (pin30) and tie chip_select to VCC
• Remove RAM bank select, only use 64K of the 128K RAM. Cut bank15 and bank16 and tie bank15 to VCC, bank16 to A15.
• Reroute RAM's write_enable to CPLD so write can be qualified with clock. Cut write_enable (pin29) of RAM and connect it to T8

• Free up connections to CPLD Lab H to allow better routing inside CPLD. Cut HSYNC and route T15 to HSYNC
• Cut out signals, nNMI, RAMA15, RAMA16 to enable routing.