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Table of Contents
CPLD Educational Board with 6502/Z80 Processor, CPLD6502 Rev 1
Introduction
CPLD Trainer explores the world of complex programmable logic device (CPLD) and how it interact with 6502, Z80, and other processor and memories. Discussion about the CPLD trainer can be found here. This is the link to previous version (rev0) of CPLD trainer.
Features
Design Files
Z80 Implementation
Z80 implementation requires 14.7MHz oscillator, CMOS Z80, 512K RAM (e.g. AS6C4008), and 512K flash (e.g. SST39SF040)
Z80 CPLD design file to run ROMWBW
ROMWBW program for 512K boot flash such as SST39SF040
