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builderpages:plasmo:vgarc1:vgarc1home [2023/01/28 22:05] plasmo |
builderpages:plasmo:vgarc1:vgarc1home [2023/02/10 23:08] (current) plasmo |
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| - | ====== VGARC, Text-based VGA Adapter for RC2014 ====== | + | ====== VGARC, Text-based VGA Adapter |
| ===== Introduction ===== | ===== Introduction ===== | ||
| - | VGARC, rev1 replaces the previous exploratory [[: | + | VGARC, rev1 replaces the previous exploratory [[: |
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| ===== Theory of Operation ===== | ===== Theory of Operation ===== | ||
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| + | VGARC rev1 has two interfaces, PS2 keyboard interface and VGA video interface. | ||
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| + | ==== PS2 Keyboard Interface ==== | ||
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| + | PS2 keyboard communicated to VGARC via two wires, PS2Clock and PS2Data. Data flow only from PS2 to VGARC, commands from VGARC to PS2 keyboard is not implemented. PS2Clock is a bidirectional signal between VGARC and PS2 keyboard, while PS2Data is an input from PS2 keyboard to VGARC. In idle state both PS2Clock and PS2Data are high. When a key is pressed, PS2 keyboard serially transmit data on PS2Data line and strobe PS2Clock for each data bit. Once a full byte of keyboard data is received with correct parity, the data is stored in hold register at location 0xF4 and least significant bit of 0xF5 is set to indicate keyboard data ready. VGARC pull down PS2Clock to prevent further transmission of keyboard data. Once Z80 read the keyboard data in hold register, the status bit is cleared and PS2Clock is negated to allow more incoming data from PS2 keyboard. \\ There are two I/O registers associated with PS2 keyboard; PS2 data register is a read-only 8-bit register located at I/O address 0xF4 located. PS2 status register is read-only with bit 0 set to indicate data ready and bit 0 cleared to indicate no data. Bit 1 to bit 8 of PS2 status register are same values as bit 1 to bit 7 of PS2 data register. PS2 status bit is cleared when PS2 data is read. | ||
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| + | ==== VGA Video Interface ==== | ||
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| + | The VGA video interface is comprised of a 4K dual-port RAM and VGA timing generator in CPLD. One side of the dual-port RAM is connected to RC2014 bus as 4K of I/O space with default addresses of 0x0-0xF; the 4K space is divided into 3K of text memory (I/O addresses 0x0-0xB) and 1K of font tables (addresses 0xC-0xF). The other side of the dual-port RAM is accessible by the CPLD video generator only. The video generator continuously read the 3K text memory sequentially starting from the first location to end of 3K memory; the text value is used to look up the corresponding font table located at the top 1K of the dual-port RAM; and the bit patterns from the font table is loaded into a shift register that shifts data out at 25.175MHz pixel rate. | ||
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| + | The video display is 64 columns and 48 row of monochrome texts organized as follow: the 1st video RAM location corresponds to character at the upper leftmost corner of the display, i.e. first character of the first line; next location is 2nd character of the first line; 64th video RAM location is the last character of the first line; 65th video RAM location is first character of the 2nd line; and 3072th location is the last character of the 48th line. Video memory can be written anytime without snowing, flicking or other undesirable display artifacts. Font lookup tables start from dual port RAM location 3073-4096 such that locations 3073 to 3080 is the font table for character value 0x0; and locations 4089-4096 is the font table for character value 0x7F. Each byte of the 8-byte font table represents 8 pixels of a 8×8 pixel character graphic such that first font byte is the top 8 pixels and 8th font byte is the bottom 8 pixels of a character graphic; most significant bit is leftmost pixel while least significant bit is rightmost pixel. To make the text more readable, the VGA controller generates 2 blank pixel lines between each row of characters. This way the font table graphic can be as large as 7 pixel wide, 8 pixel tall and not merge with the characters above or below the current line. Font table can be updated anytime. | ||
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| + | Two recently added functions are inverse video font and hardware scrolling. inverse video font is the inverse of standard 128 fonts. Inverse video font is activated by setting bit 8 of a text. (Text is 7-bit mapped to 128 fonts, the 8th bit was not used previously.) The second added functions is hardware scrolling that is accomplished by writing values 1 to 47 to a register to scroll up screen text by 1 to 47 rows. The rows scrolled off the top of screen are roll around to to the bottom of the screen. For a typical console application, | ||
| ===== Design Information ===== | ===== Design Information ===== | ||
| - | Schematic | + | {{: |
| - | Gerber photoplots | + | {{: |
| - | CPLD design | + | {{: |
| ==== Software ==== | ==== Software ==== | ||
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