Development

Version 001a

23/3/2021 Circuit design drafted, board layout draft, proceeding to prototype.

31/3/2021 SN76489s prototyped and working. VGM files play.

1/4/2021 12Mhz wouldn't work. Tried adding clock switch code. Turned out had bad SN76489, 74LS245.

3/4/2021 YM2612 prototyped. Fakes chips :( Realized need a clock divider. Added. Space very tight now. Changed port decoding. Added jumper to disable wait signal for interrupt driven driver. Identified some test code.

Version 001b

Change name to SBC-VGM since this is a bit esoteric and the SND moniker should probably be reserved for a more generic design.

6/4/2021 Routed digital section.

3/10/2021 Delayed due to inability to get genuine YM2612 parts and work on DMA and 4PIO board. Rerouted using Freerouting. Ordered YM3834 to continue developement.

7/11/2021 Verson 001b has been build and tested with a YM3834. Issue 1 GND and VCC not connected to U6. Issue 2 R18 & R19 incorrectly connect to wrong input on the TL072. Issue 3 Footprints for small capacitors too big. Issue 4 C20 & C21 too close to speaker terminals. Issue 5 1000uF C20 & C21 physically too large. VGMPLAY software working on YM and SN chip.

Version 001c

Board rerouted with above corrections. Adjustments to capacitors. Addition of vent hole under YM2612. Routing refinements. Found out two of my 4 “fake” YM2612's were actually real :)

Errata

Version 001b

~~U6 - VCC not connected - Bridge pins 13 and 14 on the PCB side~~

~~U6 - GND not connected - Link pin 7 to pin 11 on the PCB side (or to pin C32 on the ECB connector)~~

U6 is not required. Remove and link pins 3 & 5

R18 and R19 incorrect connection - With both, solder in the end at the PCB edge. Link the free end of R18 to the PCB edge end of R16. Link the free end of R19 to the PCB end of R17. Both links done on the component side.

C6 - Change to 100uF (for commonality)

C5 - Change to 470uF

Version 001c

U6 is not required. Remove and link pins 3 & 5

Key Learnings

SN76489

Mono output. Two devices required for stereo output.
Write only. Cannot probe for existence.
No reset or power on initialization.
Sound needs to be turned off at boot or clock blocked at startup.
Incorrect write can cause READY signal to stay low causing a wait state lockup.
Original Sega Genesis clock is 3579545Hz for NTSC systems and 3546893Hz for PAL
Data sheet has a reverse interpretation of D0-D7 order. Kicad symbol uses standard representation.