Up and runnin, mostly, also notes on standard ttl fanout and propagation issues

[Vince Mulhollon <vi...@mulhollon.com>]

Good Afternoon,

WRT the reports that standard original TTL won't work on the SBCv2, last weekend before my last ALS family chips arrived, I tried my board out anyway with some vintage TTL from the junkbox and did some troubleshooting with my scope.  After all, what do I have to lose but a tiny bit of socket wear  and some patience?

I believe I've isolated a fanout / fanin problem where a LS inverter in the reset circuitry can't pull the active low reset, low enough if numerous standard TTL chips are on the board.  The lowest it could drag while I held the switch down was somewhat over 2 volts, which is pretty marginal.  I fooled around with shorting to ground while low (which is technically OK for TTL...) and that didn't help very much.  I would imagine having the reset ckt drive a discrete transistor of virtually any beta would be sufficient to eliminate this.  Or, just do like people say and don't use standard TTL.  Or in retrospect I should have substituted in a standard inverter for the LS, from memory I think standard used to be able to sink some multiple the current of a LS.

As for prop delays while poking around w/ the scope I think the critical path for standard TTL is via the or gates not being fast enough to feed the latches.  4 MHz was fairly hopeless.  When I yanked the 1.8... MHz uart osc and used it to run the main clock instead, then depending on which individual standard TTL 7432 fed which individual standard ttl memory latch I got weird results, wish I had taken better notes but it certainly looked weird on the scope.  I wonder if I had fed it with 1 MHz or less if it would have worked with standard TTL, aside from the fanout problem above.

In retrospect I also wish I had taken better notes, and taken current level measurements of different families.

Anyway my ALS family order finally arrived, and after swapping chips such that I've now got a mostly ALS board, I can see on the bus monitor card on the most significant bits of the address lines its obviously doing some manner of mem test or copying at RomWBW boot time (really fast) and putting my scope on the RS232 side of the tx path of the max232 I see a second or so after reset its obviously squirting some kind of boot message, pausing, and sending some more RS-232 chars.  So I'm 99.9% up just need to solder up a rs232 to 5x2 cable and scavenge a USB-to-232 dongle and some hardware mounting stuff and I'll be up and running.  So I celebrated by ordering a diskIO and color VDU and other boards today from Andrew...

I've already messed up the pins on one eprom, so I'm also going to do the "stack some sockets and stick a ZIF on top" thing.

Thanks!