Hi Dave! Thanks! Agree 100%
lets discuss some design concepts and see what sorts
out. Given the scope of this project we need to
think this through before launching and really
examine the assumptions.
Yes, there are many Intel/Zilog
designs already and I agree the 68K architecture ISA
is much nicer and cleaner than the x86. I
especially like the 68040 since it has the MMU and
FPU built in. However I am trying to keep an open
mind on the 68K vs x86 because there may be some
major hardware advantages to the x86 side (386EX for
example). In either case the key will be
interfacing the RAM SIMM, boot ROM, and IO
Propellers.
Agree the Propellers won’t be
able to keep up with the CPU clock speed assuming it
is 16-20 MHz. However I am thinking we can decouple
the Propeller cogs from the CPU bus by latching the
pins. Something like a pair of 74LS373s to latch
the CPU data bus pins to and from the IO data bus
and another 74LS373 to latch the control pins (CS,
PropReady, etc) between the two. Then the CPU can
poll the IO latches rather than the Propellers
themselves. This *should* simplify the PASM
required as well since it would reduce the timing
dependencies.
I am not fixated on the
Propellers either but they are the most capable
hobbyist friendly IO controllers I am aware of.
Where else can you get a VGA display, PS/2 keyboard,
and microSD in one 40 pin DIP plus a few passives?
That’s enormous density and seems like a natural fit
to me. They are not perfect though as they only
really are VGA text capable.
Due to the complexity of the bus
interface logic and sheer quantity of data and
address pins the use of programmable logic devices
may be unavoidable with a 68040 CPU especially if we
want to keep the PCB affordable so I can see where
this is headed – either FPGA or CPLD for the glue
logic. That’s a bit of disappointment but we may
yet be able to use PTH components so at least we
avoid SMT and its issues.
There are still a selection of
CPLDs in the PLCC 84 format. It may require two
chips for all the pins though with some sort of
split between the pins like IO vs memory busses.
The 68040, the RAM SIMM, and the boot ROM are
already PTH components.
http://www.jameco.com/webapp/wcs/stores/servlet/Product_10001_10001_1724211_-1
Jameco part number 1724211 (not cheap but we may be
able to do better)
Thanks and have a nice day!
Andrew Lynch
Hi Andrew
Hi I would be very interested
in helping on this as I am pretty familiar with
68K now and of course the propeller as well. I
think the propeller would is going to be a
challenge especially at higher frequencies. The
Lava board has gotten me interested in other
approaches as well. The I/O on the propeller is
pretty limiting at the moment - the prop II
whenever it becomes available would be a better
fit. Believe it or not (I know it is
sacreligious) I have started play with the Xilinx
Spartan FPGA that is used on the Lava board - I
think there is promise for something like that -
maybe we can have a breakout board that would plug
in that has it mounted (as I know a lot of
builders don't want to get into SMT technology - I
am started to get the hang of it).
I think we have enough Intel
boards in the world and I really like the 68xxx
programming model much better than Intel. We
should start throwing some design ideas around and
see what we can come up - I am happing to do some
bread boarding where possible.