RE: [N8VEM: 2529] Re: Disk-I/O -- Tonight's Testing Progress

["Andrew Lynch" <lyn...@yahoo.com>]

Hi Max!  You might save a little time if you use the spare OR gate on the
Disk IO board (IC5) and you could cobble an OR gate using one of the spare
74LS27 gates with one of the spare 74LS06 inverters and a pull up resistor.

That way you won't need to fabricate a new prototype board for the OR gate
and you could do it all using components on the Disk IO board.

I hope this helps!  Thanks and have a nice day!

Andrew Lynch

> -----Original Message-----
> From: n8...@googlegroups.com [mailto:n8...@googlegroups.com] On Behalf Of
> Max Scane
> Sent: Thursday, February 12, 2009 4:53 PM
> To: N8VEM
> Subject: [N8VEM: 2529] Re: Disk-I/O -- Tonight's Testing Progress
> 
> 
> Hi Michael,
> 
> Thanks for the info.  I will have a look at that.
> 
> What I'm trying to prevent is suspected invalid read and write strobes
> being sent to the drive when neither of the CS lines are asserted.  My
> thought is that the drive is seeing that as a read or write to a non
> existent register set.
> 
> Looking at the diagram, it looks like IDE /CS0 is asserted before IDE /
> RD and IDE /WR and continues until after they are de-asserted.  So if
> I use CSx to gate the /RD and /WR signals I should be ok I think.
> 
> Regards,
> 
> Max.
> 
> On Feb 13, 8:08 am, Michael Haardt <mic...@moria.de> wrote:
> > > I have a hunch that the WD drive doesn't like getting data strobes
> > > (DIOR, DIOW) without a valid CS being active.  Normally if you are
> > > using a peripheral chip and you don't assert the CS line the chip
> > > ignores anything applied to its bus lines. You would think that that
> > > would be so for the IDE also.
> >
> > > What I will have to doto prove or disprove my theory is to make up a
> > > small module that sits in between the drive and the Disk IO board that
> > > gates the DIOR and DIOW signals with the two CS signals.
> >
> > I looked around the web for IDE interfaces and this explains the
> > timing pretty nice:
> >
> >  http://www.retroleum.co.uk/ide_interface.html
> >
> > Simply gating the signals with /CS does not fulfill the timing
> > requirements, because they will be too early, when the address lines
> > are not stable yet.
> >
> > If I read the schemtics right, /IORQ is part of /CS.  That delays /CS a
> > lot.  How about gating /RD and /WR with /IORQ, and removing /IORQ from
> the
> > /CS generation? The Z80 timing as such looks fine for an IDE interface.
> >
> > Michael
>