Re: Disk-I/O -- Tonight's Testing Progress

[lynchaj <lyn...@yahoo.com>]

Hi Max!  I checked the IDE /CS1FX and /CS3FX signals with the logic
probe.  It seems to be normal as it is high with a pulse when trying
to read from the IDE registers from the RAM monitor.

>i
27 FF

>i
2f FF

When I try the same thing using the XT-IDE board and DEBUG I get a
value of $50 from the status register which is what you'd expect.

I am back to the timing theory.  Probably the sequencing is just not
proper enough to allow latching.

Thanks and have a nice day!

Andrew Lynch


On Feb 14, 10:02 am, lynchaj <lyn...@yahoo.com> wrote:
> Hi Max!  I was thinking some more about the Disk IO IDE interface and
> have a new theory.
>
> The WD drives are acting like they are not being stuck in the
> tristate.  We need the chip selects to work properly to get the WD
> drive to respond.
>
> Notice the /CS1FX and /CS3FX pins on the WD IDE drive are driven by a
> plain 74LS32.   It is possible that a regular TTL part may not have
> sufficient drive capacity.
>
> From the 74LS32 datasheet, Ioh is -0.8 mA and Ioi is 16 mA.  I wonder
> if the WD drives just take more current source/sink than that to work
> properly.
>
> On the XT-IDE interface it uses a 74LS573 which has a lot more current
> source/sink capacity and it has no problem with the WD drives.
>
> Its an idea.  I will be testing some more today since the XT-IDE
> project is on hold right now.
>
> Thanks and have a nice day!
>
> Andrew Lynch
>
> On Feb 14, 3:03 am, Max Scane <mjs...@gmail.com> wrote:
>
>
>
> > Not Yet. Haven't had any time to play.  Should be able to look at it
> > soon though..
>
> > Max.
>
> > On Feb 14, 11:46 am, "Andrew Lynch" <lyn...@yahoo.com> wrote:
>
> > > Hi Max!  Thanks!  Any luck with your testing?  I reconfigured my Disk IO
> > > board to have similar pull up/pull down resistors as the XT-IDE controller
> > > and still I cannot read registers with the WD drive.  Since a similar
> > > configuration on the XT-IDE works on the WD drive I think we can safely
> > > assume that the pull up/pull down resistors most likely are not the issue.  
>
> > > Probably your theory of the timing relationship is the correct one but only
> > > experimentation will find out for sure.  If it is timing related we could
> > > gate the /WR and /RD pins to improve the performance.
>
> > > Thanks and have a nice day!
>
> > > Andrew Lynch
>
> > > > -----Original Message-----
> > > > From: n8...@googlegroups.com [mailto:n8...@googlegroups.com] On Behalf Of
> > > > Max Scane
> > > > Sent: Thursday, February 12, 2009 4:53 PM
> > > > To: N8VEM
> > > > Subject: [N8VEM: 2529] Re: Disk-I/O -- Tonight's Testing Progress
>
> > > > Hi Michael,
>
> > > > Thanks for the info.  I will have a look at that.
>
> > > > What I'm trying to prevent is suspected invalid read and write strobes
> > > > being sent to the drive when neither of the CS lines are asserted.  My
> > > > thought is that the drive is seeing that as a read or write to a non
> > > > existent register set.
>
> > > > Looking at the diagram, it looks like IDE /CS0 is asserted before IDE /
> > > > RD and IDE /WR and continues until after they are de-asserted.  So if
> > > > I use CSx to gate the /RD and /WR signals I should be ok I think.
>
> > > > Regards,
>
> > > > Max.
>
> > > > On Feb 13, 8:08 am, Michael Haardt <mic...@moria.de> wrote:
> > > > > > I have a hunch that the WD drive doesn't like getting data strobes
> > > > > > (DIOR, DIOW) without a valid CS being active.  Normally if you are
> > > > > > using a peripheral chip and you don't assert the CS line the chip
> > > > > > ignores anything applied to its bus lines. You would think that that
> > > > > > would be so for the IDE also.
>
> > > > > > What I will have to doto prove or disprove my theory is to make up a
> > > > > > small module that sits in between the drive and the Disk IO board that
> > > > > > gates the DIOR and DIOW signals with the two CS signals.
>
> > > > > I looked around the web for IDE interfaces and this explains the
> > > > > timing pretty nice:
>
> > > > >  http://www.retroleum.co.uk/ide_interface.html
>
> > > > > Simply gating the signals with /CS does not fulfill the timing
> > > > > requirements, because they will be too early, when the address lines
> > > > > are not stable yet.
>
> > > > > If I read the schemtics right, /IORQ is part of /CS.  That delays /CS a
> > > > > lot.  How about gating /RD and /WR with /IORQ, and removing /IORQ from
> > > > the
> > > > > /CS generation? The Z80 timing as such looks fine for an IDE interface.
>
> > > > > Michael- Hide quoted text -
>
> > - Show quoted text -- Hide quoted text -
>
> - Show quoted text -