RE: [N8VEM: 129] Adding CP/M in Rom

["Andrew Lynch" <lyn...@yahoo.com>]

> -----Original Message-----
> From: n8...@googlegroups.com [mailto:n8...@googlegroups.com] On Behalf Of
> Dan Roganti
> Sent: Sunday, June 22, 2008 10:06 PM
> To: N8VEM
> Subject: [N8VEM: 129] Adding CP/M in Rom
> 
> 
> Andrew,
> 
> I liked the idea about CP/M in Rom so much that I wanted to try and
> add this to my existing S-100 systems. I suppose this would would be
> off-topic for this group list
> I'm far behind in rebuilding my floppy drives that have been in
> storage. It would be really nice to have a systems running with CP/M
> and get to experience this again. Then I can contemplate on floppy
> drive issue later on.
> I've been reviewing your website little by little about how it's done
> in your design and looking into how I can port this into my system. At
> the moment the biggest prom card I have is 32KB (16x 2716's). Any info
> you can provide would be great.
> 
> thanks
> =Dan
> 
> [AJL>] 
Hi Dan,

If you want a ROM card to boot CP/M I think it may be easiest to make it
yourself using a prototype board.  All you need is a 27C256 EPROM, a 74LS273
style latch, and an IO address decoder.

The IO port would be for ROM enable/disable.  The 27C256 would be for 32Kx8
EPROM.  You can store a boot loader and a CP/M image in there easily.
However, if you want the ROM disk feature you'll need a larger EPROM and use
the remaining 74LS273 latch bits for extended addressing.

Making a boot loader is pretty simple.  You'll need to configure your CPU
board to set its Power-On-Reset vector to the EPROMs starting address.  All
the boot loader does is copy the CP/M boot image (CCP+BDOS+CBIOS) to the
CP/M starting address and then passing control to it.  The CBIOS boot
routine will then switch out the ROM.

You can see how the whole thing works by reading the various program source
code in the N8VEM website.  The toughest part will be to write the CBIOS
code although you can use mine as a prototype.

One final thing, you need to make sure there is a "window" in memory for the
ROM to be seen by the CPU through.  Somehow the CPU has to see the ROM on
start up or RESET so it can take control and not have bus contention with
RAM or other IO ports.

Thanks and have a nice day!

Andrew Lynch