| Core Statistics |
| Core Type=blk_mem_gen_v7_3 |
| c_addra_width=10 |
c_addrb_width=10 |
c_algorithm=1 |
c_axi_id_width=4 |
| c_axi_slave_type=0 |
c_axi_type=1 |
c_byte_size=9 |
c_common_clk=0 |
| c_default_data=0 |
c_disable_warn_bhv_coll=0 |
c_disable_warn_bhv_range=0 |
c_elaboration_dir=masked_value |
| c_enable_32bit_address=0 |
c_family=spartan6 |
c_has_axi_id=0 |
c_has_ena=0 |
| c_has_enb=0 |
c_has_injecterr=0 |
c_has_mem_output_regs_a=0 |
c_has_mem_output_regs_b=0 |
| c_has_mux_output_regs_a=0 |
c_has_mux_output_regs_b=0 |
c_has_regcea=0 |
c_has_regceb=0 |
| c_has_rsta=0 |
c_has_rstb=0 |
c_has_softecc_input_regs_a=0 |
c_has_softecc_output_regs_b=0 |
| c_init_file=BlankString |
c_init_file_name=fname.mif |
c_inita_val=0 |
c_initb_val=0 |
| c_interface_type=0 |
c_load_init_file=1 |
c_mem_type=3 |
c_mux_pipeline_stages=0 |
| c_prim_type=1 |
c_read_depth_a=1024 |
c_read_depth_b=1024 |
c_read_width_a=8 |
| c_read_width_b=8 |
c_rst_priority_a=CE |
c_rst_priority_b=CE |
c_rst_type=SYNC |
| c_rstram_a=0 |
c_rstram_b=0 |
c_sim_collision_check=ALL |
c_use_bram_block=0 |
| c_use_byte_wea=0 |
c_use_byte_web=0 |
c_use_default_data=1 |
c_use_ecc=0 |
| c_use_softecc=0 |
c_wea_width=1 |
c_web_width=1 |
c_write_depth_a=1024 |
| c_write_depth_b=1024 |
c_write_mode_a=WRITE_FIRST |
c_write_mode_b=WRITE_FIRST |
c_write_width_a=8 |
| c_write_width_b=8 |
c_xdevicefamily=spartan6 |
| Core Type=blk_mem_gen_v7_3 |
| c_addra_width=11 |
c_addrb_width=11 |
c_algorithm=1 |
c_axi_id_width=4 |
| c_axi_slave_type=0 |
c_axi_type=1 |
c_byte_size=9 |
c_common_clk=1 |
| c_default_data=0 |
c_disable_warn_bhv_coll=0 |
c_disable_warn_bhv_range=0 |
c_elaboration_dir=masked_value |
| c_enable_32bit_address=0 |
c_family=spartan6 |
c_has_axi_id=0 |
c_has_ena=0 |
| c_has_enb=0 |
c_has_injecterr=0 |
c_has_mem_output_regs_a=0 |
c_has_mem_output_regs_b=0 |
| c_has_mux_output_regs_a=0 |
c_has_mux_output_regs_b=0 |
c_has_regcea=0 |
c_has_regceb=0 |
| c_has_rsta=0 |
c_has_rstb=0 |
c_has_softecc_input_regs_a=0 |
c_has_softecc_output_regs_b=0 |
| c_init_file=BlankString |
c_init_file_name=no_coe_file_loaded |
c_inita_val=0 |
c_initb_val=0 |
| c_interface_type=0 |
c_load_init_file=0 |
c_mem_type=2 |
c_mux_pipeline_stages=0 |
| c_prim_type=1 |
c_read_depth_a=2048 |
c_read_depth_b=2048 |
c_read_width_a=8 |
| c_read_width_b=8 |
c_rst_priority_a=CE |
c_rst_priority_b=CE |
c_rst_type=SYNC |
| c_rstram_a=0 |
c_rstram_b=0 |
c_sim_collision_check=ALL |
c_use_bram_block=0 |
| c_use_byte_wea=0 |
c_use_byte_web=0 |
c_use_default_data=0 |
c_use_ecc=0 |
| c_use_softecc=0 |
c_wea_width=1 |
c_web_width=1 |
c_write_depth_a=2048 |
| c_write_depth_b=2048 |
c_write_mode_a=WRITE_FIRST |
c_write_mode_b=WRITE_FIRST |
c_write_width_a=8 |
| c_write_width_b=8 |
c_xdevicefamily=spartan6 |
| Core Type=blk_mem_gen_v7_3 |
| c_addra_width=13 |
c_addrb_width=13 |
c_algorithm=1 |
c_axi_id_width=4 |
| c_axi_slave_type=0 |
c_axi_type=1 |
c_byte_size=9 |
c_common_clk=0 |
| c_default_data=FF |
c_disable_warn_bhv_coll=0 |
c_disable_warn_bhv_range=0 |
c_elaboration_dir=masked_value |
| c_enable_32bit_address=0 |
c_family=spartan6 |
c_has_axi_id=0 |
c_has_ena=0 |
| c_has_enb=0 |
c_has_injecterr=0 |
c_has_mem_output_regs_a=0 |
c_has_mem_output_regs_b=0 |
| c_has_mux_output_regs_a=0 |
c_has_mux_output_regs_b=0 |
c_has_regcea=0 |
c_has_regceb=0 |
| c_has_rsta=0 |
c_has_rstb=0 |
c_has_softecc_input_regs_a=0 |
c_has_softecc_output_regs_b=0 |
| c_init_file=BlankString |
c_init_file_name=fname.mif |
c_inita_val=0 |
c_initb_val=0 |
| c_interface_type=0 |
c_load_init_file=1 |
c_mem_type=3 |
c_mux_pipeline_stages=0 |
| c_prim_type=1 |
c_read_depth_a=8192 |
c_read_depth_b=8192 |
c_read_width_a=8 |
| c_read_width_b=8 |
c_rst_priority_a=CE |
c_rst_priority_b=CE |
c_rst_type=SYNC |
| c_rstram_a=0 |
c_rstram_b=0 |
c_sim_collision_check=ALL |
c_use_bram_block=0 |
| c_use_byte_wea=0 |
c_use_byte_web=0 |
c_use_default_data=1 |
c_use_ecc=0 |
| c_use_softecc=0 |
c_wea_width=1 |
c_web_width=1 |
c_write_depth_a=8192 |
| c_write_depth_b=8192 |
c_write_mode_a=WRITE_FIRST |
c_write_mode_b=WRITE_FIRST |
c_write_width_a=8 |
| c_write_width_b=8 |
c_xdevicefamily=spartan6 |
| Core Type=clk_wiz_v3_6 |
| clkin1_period=31.25 |
clkin2_period=31.25 |
clock_mgr_type=AUTO |
feedback_source=FDBK_AUTO |
| feedback_type=SINGLE |
manual_override=false |
num_out_clk=1 |
primtype_sel=DCM_SP |
| use_clk_valid=false |
use_dyn_phase_shift=false |
use_dyn_reconfig=false |
use_freeze=false |
| use_inclk_stopped=false |
use_inclk_switchover=false |
use_locked=false |
use_max_i_jitter=false |
| use_min_o_jitter=false |
use_phase_alignment=false |
use_power_down=false |
use_reset=false |
| use_status=false |