Home » RBC Forums » General Discussion » General Instrument CTS256A-AL2 vs. Microchip CTS256AL2
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| Re: Reverse-Engineering the Speech Processor ROM [message #10696 is a reply to message #10692] |
Wed, 10 April 2024 20:40   |
jayindallas
Messages: 110
Registered: June 2021
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As you will be working on a 70x1 first, I'll post the timing information and the mapping modes as they apply to the 70x1. The information is awkwardly available in the the TMS7000 Family Data manual. You have to look in the 5 page Appendix C and then flip back to an applicable table from the 70x0 or 70x2 sections. I'll unravel the page-flipping nonsense and type up a complete 70x1 listing. Later I'll use that to do one for the 70x0 and 70x2.
I've got the 70x2 Microprocessor Interface Mode spreadsheet mostly done. I'll quickly make a 70x1 version since you'll be using that soon. Later I'll make a 70x2 version also.
The spreadsheet allows you to enter a crystal frequency and recalculate for parameter timings (all the formulas are based on the crystal frequency after the 7000 series Divide-By-Two oscillator input circuit.
I'll be busy for about a week and a half, but I'll generate and post this stuff in parts, when I need a distraction from everything else.
Anything involving the TSM7000 I'll post on the CTS titled discussion thread. Any SP & SPR will be on the thread about reverse engineering the SPO...
[Updated on: Thu, 11 April 2024 00:44] Report message to a moderator |
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| Re: Reverse-Engineering the Speech Processor ROM [message #10699 is a reply to message #10696] |
Thu, 11 April 2024 09:56 |
lynchaj
Messages: 1080
Registered: June 2016
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Hi Jay
Which TMS7000 family data manual are you using? I am using the 1983 edition and Appendix C is something completely different (TMS7500 encryption module?)
Would like to follow along on the timing discussion. I fear there is something about the conversion from internal ROM to external ROM that I do not understand.
Is this related to the divide-by-4 vs. divide-by-2 external crystal? Aren't all the calculations done based on the normalized clock_out signal?
[Updated on: Fri, 12 April 2024 04:36] Report message to a moderator |
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| Re:TMS700x Memory Interface Mode Timing Spreadsheet UPDATE [message #10706 is a reply to message #10699] |
Fri, 12 April 2024 08:16 |
jayindallas
Messages: 110
Registered: June 2021
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Re: ...to follow along on the timing discussion...
I understand what you're talking about... the databook documentation is a bit contorted in the area of various modes and resulting memory maps etc.
However I found a section of the '86 databook that puts that into good diagrams. If I can find sections for the x0,x1,x2 then I'll sort it out and post it as 70xx notes.
Spreadsheet for Micrprocessor Interface Mode - Memory Interface Timing:
Below, is a screen capture and I'll add some comments will appear below it on how it operates and some enhancements I'm considering.
The errors in the spreadsheet above will soon be corrected. Symbol #16 had an "EL" for Enable# LOW with a description "Enable# rise" that was corrented in the '89 Manual. Also in some of the lower formulas the multiplier is 1.5 x Tc(C) and not 0.5 x Tc(C).
This spreadsheet is based on a section about Microprocessor Interface Mode (external Memory), "Table 9-2. Memory Interface Timing" that appears on Page 9-5 in the 1986 TMS 7000 Series Databook.
For the 70x1 in Microprocessor Interface Mode -- Memory Interface Timing, Appendix C refers using the timing for the 70x0. That chart is not consistent with the 70x2 so I'll have to make a separate spreadsheet for the combined 70x0/70x1.
The Data Book I'm Using (reference to Appendix C)
I have the TMS7000 series documents listed below. I'm using a paperback version I used at Tandy Electronic Design (TED) back around '86 to '89.
ITEM-1 :: "TMS7000 Family Data Manual" | publication ID "SND001B" | version "June 1986, Revision B"
Updated these bitsavers.org links 2024/04/19:
https://bitsavers.org/components/ti/TMS7000/SPND001B_TMS7000 _Family_Data_Manual_1986.pdf
NOTE: The Link/URL above is a PDF of the same paperback databook I'm using; you should find the Appendix C with the TMS70x1 references I've mentioned.
I'm going to look at this 1989 databook to look for corrections or improved data:
https://bitsavers.org/components/ti/TMS7000/SPND001C_TMS7000 _Family_Data_Manual_1989.pdf
I've reconstructed part of a lost message here from a few days ago...
Its an index of all relevant SP & SPR pages in the GI 1982 Microelectronics PDF.
PAGE DOCUMENT PART COMMENTS OR
OFFSETS PAGE ID NUMBER DESCRIPTION
------- -------- ----------- -------------------------
76 2-63 INDEX AUDIO :: Speech ROMs
77 2-64 SPR016 2Kx8 Serial Read Only Memory (ROM)
83 2-70 SPR032 4Kx8 Serial Read Only Memory (ROM)
86 2-73 SPR128 16K Serial Read Only Memory (ROM) [i]Preliminary[/i]
284 5-3 INDEX AUDIO :: Speech Synthesis
286 5-5 SP0256 Narrator(tm) Speech Processor
290 5-9 SP0256-AL2 Allophone Based Speech Processor
290 5-9 SP0232 32K Speech Processor [i]For future release[/i]
290 5-9 SPR000 Speech Interface Chip
...designed to interface a standard ROM, PROM, or EPROM
to the SPO256 Speech Processor...
291 5-10 VSM2032 ...eight TTL compatible signals are used to select the
spoken phrase. Once selected, the VSM2032 requires no
support from the user's circuit...
293 5-12 SP0250 Speech Synthesizer
296 5-15 SFD2000 Speech Field Development Board
...Its is used to demonstrate and test synthetic speech
or complex sounds before they are committed to masked Rom.
Its proof that your Daisy256 concept can work after finding all hurdles.
[Updated on: Tue, 23 April 2024 18:03] Report message to a moderator |
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| Re: What TMS7000 Family Data Manual Version Am I Using? [message #10709 is a reply to message #10706] |
Fri, 12 April 2024 13:54 |
lynchaj
Messages: 1080
Registered: June 2016
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Senior Member |
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Hi Jay
Holy Mackerel! The SPR000 is *exactly* what's needed to add custom firmware to the SPR0256! It is a hardware chip to do exactly that! No MCU or CPLD needed.
eBay has some and there are some being sold by other vendors. However, I can't find a real datasheet so I don't have a pinout. Do you have or know where to get a datasheet or excerpt from a data book on the SPR000? My goodness, I had no idea such a thing existed.
Wow!
Also, a scan of the "Speech Field Development Data Manual" would probably be sufficient as well
It would be ironic if I can find the hardware but not the datasheet. Usually it is the other way around.
[Updated on: Fri, 12 April 2024 14:32] Report message to a moderator |
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| Re: What TMS7000 Family Data Manual Version Am I Using? [message #10721 is a reply to message #10709] |
Fri, 19 April 2024 03:37 |
lynchaj
Messages: 1080
Registered: June 2016
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Hi
The DAISY256 PCBs arrived yesterday and I will start building probably tomorrow morning. I would like to get it assembled and test out the control case (CTS256 + SP0256).
Assuming that works, I'll move on to experimenting with the TMS7001 & 2732 EPROM. Let's hope this works.
I think it will open a whole new chapter in CTS256 by allowing custom firmware and also bringing long needed new parts into availability. Maybe a CTS256 renaissance?
Let me know if you're interested in building your own board. The default build is essentially a mecparts Talker text-to-speech so even if the experiment fails, you still have a TTS board.
Thanks, Andrew Lynch
[Updated on: Fri, 19 April 2024 03:38] Report message to a moderator |
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| DAISY256 works [message #10722 is a reply to message #10721] |
Mon, 22 April 2024 03:36 |
lynchaj
Messages: 1080
Registered: June 2016
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Hi
Now we know DAISY256 works. I tested initially with CTS256 and SP0256 in a traditional TTS configuration and it works fine. Then I tested it with the CTS256 using external firmware and that also works well. I verified the external firmware EPROM is being accessed with my logic probe.
Finally, I tested the TMS7001 plus external EPROM and that works fairly well too. Probably not quite as reliable as the CTS256, but after reset seems to be just fine. I suspect there may be some timing issues with the reset circuit being slightly too long in TMS7001 mode. The time constant on the reset circuit is about 1 second which seems like a really long time to me. Not sure the reasoning on it.
I have some TMS70C02 and TMS77C82 chips on the way. The major differences are the CMOS chips are only clock doubled as opposed to the TMS7001 derivatives being clock quadrupled. My plan is to use a 5 MHz clock instead. Also, it appears the UART uses half the clock cycles per bit on the CMOS TMS7xCx2 versions so may either need custom firmware or possibly live with twice the speed (19200 baud vs. 9600 baud). We'll see once those parts arrive.
I did have a bad 10 MHz crystal that took a while to find but not a show stopper. I've not had a crystal go bad on me before so that was a first. Oh well, another permanent resident for the "bad parts" box.
I have a video of the test, but it won't let me upload it because it is too big (~19MB)
Thanks, Andrew Lynch
PS, I still have 4 PCBs left over since I only needed one. The build worked the first time with no bodges, cuts & jumpers, etc. If you want one of the left over PCBs please let me know and I'll send you one (US only). I would love to get some other feedback for the upcoming V1.1 version.
[Updated on: Mon, 22 April 2024 03:45] Report message to a moderator |
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| Re: DAISY256 works [message #10724 is a reply to message #10723] |
Mon, 22 April 2024 15:10 |
lynchaj
Messages: 1080
Registered: June 2016
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Senior Member |
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Hi Jay
Thankfully, we have the disassembled CTS256 source code which can be found her: https://github.com/GmEsoft/CTS256A-AL2/blob/main/CTS256A.ASM
Looking over the code, I think this is the region which determines input mode (serial or parallel) and then configures the serial port based various parameters.
We'll update the values in SCT1TB and T3DATB to account for the faster UART cycle clock and burn a new firmware boot EPROM.
Also, it looks like TI changed the serial port register locations from TMS7xx1 to TMS7xCx2 so they'll need to be updated too.
Maybe other things but most of the functionality should be unchanged. Just dropping in the TMS70C02 it boots using the legacy CTS256 firmware and gets as far as saying "O-K" so most of it seems to be fine. Although the serial ports are screwed up.
START MOV %>3A,B
LDSP ; Init stack pointer 3B-XX
MOVD %>2000,R45 ; R45 := $2000
MOVP %>AA,P0 ; P0 = IOCNT0 := 1010 1010
; Full Expansion;
; Clear INT1, INT2 and INT3 flags
MOVP %>0A,P16 ; P16 = IOCNT1 := 0000 1010
; Clear INT4 and INT5 flags
MOVP P4,B ; Read P4 = APORT
AND %>07,B ; Get Serial mode
CMP %>00,B ; Is it Parallel mode ?
; useful ?
; Jump if yes
JZ PARALL ; Start in parallel mode
AND %>7F,R10 ; Clear R10.7, indicating serial mode
MOVP P4,A ; Read P4 = APORT
AND %>08,A ; Get Selectable Serial Config flag
CMP %>00,A ; Is it set ?
; useful ?
; Jump if not
JZ SER7N2 ; Serial fixed 7N2 config
LDA @>1000 ; Read serial config from $1000
MOVP A,P17 ; Init P17 = SMODE with seria config
JMP SERSEL ; Serial selectable config
SER7N2 MOVP %>CB,P17 ; P17 = SMODE := Fixed Serial 7N2 config
SERSEL MOVP %>15,P17 ; P17 = SCTL0 := OOO1 O1O1
; Reset error flags; enable RX & TX
; A := value for SCTL1 (prescaler)
LDA @SCT1TB(B) ; Table of values for SCTL1
PUSH A
; A := value for T3DATA (timer3 reload)
LDA @T3DATB(B) ; Table of timer3 reload values T3DATA
POP B
MOVP B,P21 ; set SCTL1
MOVP A,P20 ; set T3DATA
ORP %>01,P16 ; enable T4
; proceed with RAM setup
JMP INIRAM ; Init RAM config
; Table of values for SCTL1
SCT1TB BYTE >FF,>40,>43,>40,>43,>40,>40,>40
; Table of timer3 reload values T3DATA
T3DATB BYTE >FF,>20,>57,>07,>C2,>0F,>81,>03
[Updated on: Mon, 22 April 2024 15:21] Report message to a moderator |
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| Re: DAISY256 works [message #10727 is a reply to message #10725] |
Tue, 23 April 2024 12:31 |
jayindallas
Messages: 110
Registered: June 2021
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Senior Member |
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Daisy256
The 7000 series processors tested above, are three different processor sets so three similar code sets are likely needed:
Note that there is a divide-by-2 and a divide-by-4 option on one of the processors. I think its a rom purchase, not a register settings. So be aware that some vintage 7000 series chips may require a different crystal just because its original circuit was designed with a divide-by-4.
TESTING THE TMS7041 NMOS DEVICES (all using the 70x1 serial clock rate)
Processor Set #1 The 70x1 NMOS or GI CTS running the original CTS/SP0 code.
Use '89 TMS7000 Family Data Manual, Appendix C: TMS 70x1 Devices
Testing Processor Set #1
10Mhz PIC/TMS7041 aka CTS256 and SP0256 initial test: SUCCESSFUL. Was that the Radio Shack Recommended Circuit?
10Mhz PIC/TMS7041 aka CTS256+External ROM and SP0256 test: SUCCESSFUL. That's a great indicator!
10Mhz TMS7001+External ROM and SP0256 test: SEEMS FINE AFTER RESET.
TESTING THE TMS70x2 DEVICES
Processor Set #2 The 70x2 NMOS Architecture improvements over the 70x1
Less changes between the NMOS 70x1 and the 70x2. It should be easier to convert than the conversion to CMOS; This is the way to start.
Testing Processor Set #2
5MHz TMS7002+External ROM and SP0256 test: DAISY256 SAYS "OK" BUT NOTHING AFTER THAT.
Probably needs code adjustments with timers, uart initialization, maybe interrupt detection and reset state.
Since there are many vintage 70xx chips that might be used in a board like the Daisy 256, it might be advantageous to add a trace connecting the SP0256 clock back to the 70nx so it can identify if its running at 2.5Mhz or 1.25Mhz internal clock. Firmware inside the 7xxx can do a lot to self-identify the chip and make the configuration choices without requiring a different Rom image for each possible 70nx processor. Bitsavers.org has an '83 (focus 70x1), '86 (focus 70x2) and '89 (corrections) Data Books. There are more chip numbers in the '83 Data Book that might be used to find new/old inventory. '83 had some CMOS and some 12K ROM sizes too.
TESTING THE TMS77C82 DEVICE
Processor Set #3 The 70Cx2 CMOS has many architecture improvements and changes over NMOS.
AJL is correct on CMOS requiring many more code changes. A lot of pin behavior is different of the CMOS devices; it looks like the CMOS line was following the new release market, whereas NMOS was mostly supporting existing designs.
See the '89 TMS7000 Family Data Manual, Appendix B: TMS 7000 NMOS to CMOS Conversion Guide to see how much changed and has to be reviewed to convert the code... but it would be worth the effort, as you wrote, to run it on less expensive vintage parts. Probably best to convert the NMOS x1 to the NMOS x2 first for learning-curve reasons.
Testing Processor Set #3
??MHz TMS77C82+Windowed-EProm and SP0256 test: NOTHING
Your 10Mhz to 5Mhz was clever, but CMOS versions seemed to be chasing new release markets so it was freely upgraded in contrast to NMOS devices which seemed to support existing applications.
TMS70{0,1,2} Spreadsheets
bitsavers.org has the '89 TMS 7000 Family Data Manual which is much better than the '86 manual. '89 consolidates various separate reference manuals together into one more useful manual. It also describes how to read the internal masked ROM from a TMS70xx, more clearly. The error I found in the '86 manual was corrected in the '89 manual. That involved the 70x2 spreadsheet about Microprocessor Interface Mode (aka "MIM").
The 70x2 has the best timing data in regard to MIM as its a function of Tc(C) whereas the 70x0 and 70x1 and only listed for some clock rates; however they add a TYP column for typical timing, which is useful. I've added a "TYP" typical timing field on the 70x2 MIM Spreadsheet as I'm looking for a spreadsheet construct to use that page to post the MIM Timing any 70x{0,1,2} selected. from tables on another sheet.
Efficiency by Combining Several RAM Testing, ROM Imaging and ROM Interfacing Tasks
My Read-Only Memory imaging and interfacing tasks can be efficiently combined with one Arduino setup:
(1) I have old some Random-Access Memory chips to test and validate.
(2) I have a lot of vintage system ROMs I'd like to archive into .BIN and or .HEX files and post-process some into disassembly files.
(3) I'd like to verify the GI SPRxxx serial ROMs interface, if any vintage SPR016/32 are still functional.
That's three good reasons to get an Arduino out and program it to test RAM, and read ROM chips.
I think confirming the GI SP025x-SPRxxx interface is clear enough and my arduino ROM archiving code could quickly be adapted to the emulate a SP025x-SPRxxx interface and even read any ROM code that may have been used in my TMS7000 designs. I think I have some old listings somewhere in storage that could make a quick determination which design project an EPROM was used on.
[Updated on: Thu, 23 May 2024 07:09] Report message to a moderator |
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| Baud Rate Tables for 70x1, 70x2, 70Cx2 [message #10736 is a reply to message #10734] |
Sun, 28 April 2024 21:43 |
jayindallas
Messages: 110
Registered: June 2021
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; NOTE: Some of the 70x2 and 70Cx2 could not do 50 and 110 baud.
; When a baud cannot be rendered, it is replaced with the lowest render baud rate.
; Replaced baud rates are denoted in the right margin of the baud calculation block.
;
; ____ ____ ____ ________ _______ ________ ______ ____ _____ __________ ________
; | A0 | A1 | A2 | offset | SCTL1 | T3DATA | Baud | PL | TL | Actual | Error | (Baud Table #01)
; |____|____|____|________|_______|________|______|____|_____|__________|________|
; | 0 | 0 | 0 | +0 | FFh | FFh | - - - - - Parallel Mode - - - - - | Baud Rates for:
; | 0 | 0 | 1 | +1 | 40h | 20h | 1200 | 0 | 32 | 1183.71 | -1.36% | (1) CTS256A-AL2 & 70x1 with
; | 0 | 1 | 0 | +2 | 41h | B1h | 110 | 1 | 177 | 109.73 | -0.25% | (2) divide-by-4 CLK option
; | 0 | 1 | 1 | +3 | 40h | 07h | 4800 | 0 | 7 | 4882.81 | 1.73% | (3) plus a 10 Mhz crystal
; | 1 | 0 | 0 | +4 | 43h | C2h | 50 | 3 | 194 | 50.08 | 0.16% | (4) for a 2.5 Mhz internal CLK
; | 1 | 0 | 1 | +5 | 40h | 0Fh | 2400 | 0 | 15 | 2441.41 | 1.73% |
; | 1 | 1 | 0 | +6 | 40h | 81h | 300 | 0 | 129 | 300.48 | 0.16% |
; | 1 | 1 | 1 | +7 | 40h | 03h | 9600 | 0 | 3 | 9765.63 | 1.73% |
; |____|____|____|________|_______|________|______|____|_____|__________|________|
;SCTL1 values: +0 +1 +2 +3 +4 +5 +6 +7 ; (1) CTS256A-AL2 & 70x1 with (Baud Table #01)
SCT1TB BYTE >FF,>40,>41,>40,>43,>40,>40,>40 ; (2) divide-by-4 CLK option
;T3DATA values: +0 +1 +2 +3 +4 +5 +6 +7 ; (3) plus a 10 Mhz crystal
T3DATA BYTE >FF,>20,>B1,>07,>C2,>0F,>81,>03 ; (4) for a 2.5 Mhz internal CLK
; ____ ____ ____ ________ _______ ________ ______ ____ _____ __________ ________
; | A0 | A1 | A2 | offset | SCTL1 | T3DATA | Baud | PL | TL | Actual | Error | (Baud Table #02)
; |____|____|____|________|_______|________|______|____|_____|__________|________|
; | 0 | 0 | 0 | +0 | FFh | FFh | - - - - - Parallel Mode - - - - - | Baud Rates for:
; | 0 | 0 | 1 | +1 | 40h | 0Fh | 1200 | 0 | 15 | 1220.70 | 1.73% | (1) 70x1 with
; | 0 | 1 | 0 | +2 | 40h | B1h | 110 | 0 | 177 | 109.73 | -0.25% | (2) divide-by-4 CLK option
; | 0 | 1 | 1 | +3 | 40h | 03h | 4800 | 0 | 3 | 4882.81 | 1.73% | (3) plus a 5 Mhz crystal
; | 1 | 0 | 0 | +4 | 41h | C2h | 50 | 1 | 194 | 50.08 | 0.16% | (4) for a 1.25 Mhz internal CLK
; | 1 | 0 | 1 | +5 | 40h | 07h | 2400 | 0 | 7 | 2441.41 | 1.73% |
; | 1 | 1 | 0 | +6 | 40h | 40h | 300 | 0 | 64 | 300.48 | 0.16% |
; | 1 | 1 | 1 | +7 | 40h | 01h | 9600 | 0 | 1 | 9765.63 | 1.73% |
; |____|____|____|________|_______|________|______|____|_____|__________|________|
;SCTL1 values: +0 +1 +2 +3 +4 +5 +6 +7 ; (1) 70x1 with (Baud Table #02)
SCT1TB BYTE >FF,>40,>40,>40,>41,>40,>40,>40 ; (2) divide-by-4 CLK option
;T3DATA values: +0 +1 +2 +3 +4 +5 +6 +7 ; (3) plus a 5 Mhz crystal
T3DATA BYTE >FF,>0F,>B1,>03,>C2,>07,>40,>01 ; (4) for a 1.25 Mhz internal CLK
; ____ ____ ____ ________ _______ ________ ______ ____ _____ __________ ________
; | A0 | A1 | A2 | offset | SCTL1 | T3DATA | Baud | PL | TL | Actual | Error | (Baud Table #03)
; |____|____|____|________|_______|________|______|____|_____|__________|________|
; | 0 | 0 | 0 | +0 | FFh | FFh | - - - - - Parallel Mode - - - - - | Baud Rates for:
; | 0 | 0 | 1 | +1 | 40h | 67h | 1200 | 0 | 103 | 1201.92 | 0.16% | (1) 70x2 & 70Cx2 with
; | 0 | 1 | 0 | +2 | 42h | 8Ah | 300 | 2 | 138 | 299.76 | -0.08% | (2) divide-by-2 CLK option
; | 0 | 1 | 1 | +3 | 40h | 19h | 4800 | 0 | 25 | 4807.69 | 0.16% | (3) plus a 8 Mhz crystal
; | 1 | 0 | 0 | +4 | 42h | 8Ah | 300 | 2 | 138 | 299.76 | -0.08% | (4) for a 4 Mhz internal CLK
; | 1 | 0 | 1 | +5 | 40h | 33h | 2400 | 0 | 51 | 2403.85 | 0.16% |
; | 1 | 1 | 0 | +6 | 42h | 8Ah | 300 | 2 | 138 | 299.76 | -0.08% | 50 baud replaced with 300 baud
; | 1 | 1 | 1 | +7 | 40h | 0Ch | 9600 | 0 | 12 | 9615.38 | 0.16% | 110 baud replaced with 300 baud
; |____|____|____|________|_______|________|______|____|_____|__________|________|
;SCTL1 values: +0 +1 +2 +3 +4 +5 +6 +7 ; (1) 70x2 & 70Cx2 with (Baud Table #03)
SCT1TB BYTE >FF,>40,>42,>40,>42,>40,>42,>40 ; (2) divide-by-2 CLK option
;T3DATA values: +0 +1 +2 +3 +4 +5 +6 +7 ; (3) plus a 8 Mhz crystal
T3DATA BYTE >FF,>67,>8A,>19,>8A,>33,>8A,>0C ; (4) for a 4 Mhz internal CLK
; ____ ____ ____ ________ _______ ________ ______ ____ _____ __________ ________
; | A0 | A1 | A2 | offset | SCTL1 | T3DATA | Baud | PL | TL | Actual | Error | (Baud Table #04)
; |____|____|____|________|_______|________|______|____|_____|__________|________|
; | 0 | 0 | 0 | +0 | FFh | FFh | - - - - - Parallel Mode - - - - - | Baud Rates for:
; | 0 | 0 | 1 | +1 | 40h | 5Ch | 1200 | 0 | 92 | 1202.77 | 0.23% | (1) 70x2 & 70Cx2 with
; | 0 | 1 | 0 | +2 | 43h | FDh | 110 | 3 | 253 | 110.10 | 0.09% | (2) divide-by-2 CLK option
; | 0 | 1 | 1 | +3 | 40h | 16h | 4800 | 0 | 22 | 4863.39 | 1.32% | (3) plus a 7.158908 Mhz crystal
; | 1 | 0 | 0 | +4 | 43h | FDh | 110 | 3 | 253 | 110.10 | 0.09% | (4) for a 3.579454 Mhz internal CLK
; | 1 | 0 | 1 | +5 | 40h | 2Eh | 2400 | 0 | 46 | 2379.96 | -0.83% |
; | 1 | 1 | 0 | +6 | 41h | B9h | 300 | 1 | 185 | 300.69 | 0.23% | 50 baud replaced with 110 baud
; | 1 | 1 | 1 | +7 | 40h | 0Bh | 9600 | 0 | 11 | 9321.49 | -2.90% |
; |____|____|____|________|_______|________|______|____|_____|__________|________|
;SCTL1 values: +0 +1 +2 +3 +4 +5 +6 +7 ; (1) 70x2 & 70Cx2 with (Baud Table #04)
SCT1TB BYTE >FF,>40,>43,>40,>43,>40,>41,>40 ; (2) divide-by-2 CLK option
;T3DATA values: +0 +1 +2 +3 +4 +5 +6 +7 ; (3) plus a 7.158908 Mhz crystal
T3DATA BYTE >FF,>5C,>FD,>16,>FD,>2E,>B9,>0B ; (4) for a 3.579454 Mhz internal CLK
; ____ ____ ____ ________ _______ ________ ______ ____ _____ __________ ________
; | A0 | A1 | A2 | offset | SCTL1 | T3DATA | Baud | PL | TL | Actual | Error | (Baud Table #05)
; |____|____|____|________|_______|________|______|____|_____|__________|________|
; | 0 | 0 | 0 | +0 | FFh | FFh | - - - - - Parallel Mode - - - - - | Baud Rates for:
; | 0 | 0 | 1 | +1 | 40h | 40h | 1200 | 0 | 64 | 1201.92 | 0.16% | (1) 70x2 & 70Cx2 with
; | 0 | 1 | 0 | +2 | 43h | B1h | 110 | 3 | 177 | 109.73 | -0.25% | (2) divide-by-2 CLK option
; | 0 | 1 | 1 | +3 | 40h | 0Fh | 4800 | 0 | 15 | 4882.81 | 1.73% | (3) plus a 5 Mhz crystal
; | 1 | 0 | 0 | +4 | 43h | B1h | 110 | 3 | 177 | 109.73 | -0.25% | (4) for a 2.5 Mhz internal CLK
; | 1 | 0 | 1 | +5 | 40h | 20h | 2400 | 0 | 32 | 2367.42 | -1.36% |
; | 1 | 1 | 0 | +6 | 41h | 81h | 300 | 1 | 129 | 300.48 | 0.16% | 50 baud replaced with 110 baud
; | 1 | 1 | 1 | +7 | 40h | 07h | 9600 | 0 | 7 | 9765.63 | 1.73% |
; |____|____|____|________|_______|________|______|____|_____|__________|________|
;SCTL1 values: +0 +1 +2 +3 +4 +5 +6 +7 ; (1) 70x2 & 70Cx2 with (Baud Table #05)
SCT1TB BYTE >FF,>40,>43,>40,>43,>40,>41,>40 ; (2) divide-by-2 CLK option
;T3DATA values: +0 +1 +2 +3 +4 +5 +6 +7 ; (3) plus a 5 Mhz crystal
T3DATA BYTE >FF,>40,>B1,>0F,>B1,>20,>81,>07 ; (4) for a 2.5 Mhz internal CLK
; ____ ____ ____ ________ _______ ________ ______ ____ _____ __________ ________
; | A0 | A1 | A2 | offset | SCTL1 | T3DATA | Baud | PL | TL | Actual | Error | (Baud Table #06)
; |____|____|____|________|_______|________|______|____|_____|__________|________|
; | 0 | 0 | 0 | +0 | FFh | FFh | - - - - - Parallel Mode - - - - - | Baud Rates for:
; | 0 | 0 | 1 | +1 | 40h | 3Fh | 1200 | 0 | 63 | 1200.00 | 0.00% | (1) 70x2 & 70Cx2 with
; | 0 | 1 | 0 | +2 | 42h | E8h | 110 | 2 | 232 | 109.87 | -0.12% | (2) divide-by-2 CLK option
; | 0 | 1 | 1 | +3 | 40h | 0Fh | 4800 | 0 | 15 | 4800.00 | 0.00% | (3) plus a 4.9152 Mhz crystal
; | 1 | 0 | 0 | +4 | 42h | E8h | 110 | 2 | 232 | 109.87 | -0.12% | (4) for a 2.4576 Mhz internal CLK
; | 1 | 0 | 1 | +5 | 40h | 1Fh | 2400 | 0 | 31 | 2400.00 | 0.00% |
; | 1 | 1 | 0 | +6 | 40h | FFh | 300 | 0 | 255 | 300.00 | 0.00% | 50 baud replaced with 110 baud
; | 1 | 1 | 1 | +7 | 40h | 07h | 9600 | 0 | 7 | 9600.00 | 0.00% |
; |____|____|____|________|_______|________|______|____|_____|__________|________|
;SCTL1 values: +0 +1 +2 +3 +4 +5 +6 +7 ; (1) 70x2 & 70Cx2 with (Baud Table #06)
SCT1TB BYTE >FF,>40,>42,>40,>42,>40,>40,>40 ; (2) divide-by-2 CLK option
;T3DATA values: +0 +1 +2 +3 +4 +5 +6 +7 ; (3) plus a 4.9152 Mhz crystal
T3DATA BYTE >FF,>3F,>E8,>0F,>E8,>1F,>FF,>07 ; (4) for a 2.4576 Mhz internal CLK
; ____ ____ ____ ________ _______ ________ ______ ____ _____ __________ ________
; | A0 | A1 | A2 | offset | SCTL1 | T3DATA | Baud | PL | TL | Actual | Error | (Baud Table #07)
; |____|____|____|________|_______|________|______|____|_____|__________|________|
; | 0 | 0 | 0 | +0 | FFh | FFh | - - - - - Parallel Mode - - - - - | Baud Rates for:
; | 0 | 0 | 1 | +1 | 40h | 2Eh | 1200 | 0 | 46 | 1189.98 | -0.83% | (1) 70x2 & 70Cx2 with
; | 0 | 1 | 0 | +2 | 41h | FDh | 110 | 1 | 253 | 110.10 | 0.09% | (2) divide-by-2 CLK option
; | 0 | 1 | 1 | +3 | 40h | 0Bh | 4800 | 0 | 11 | 4660.75 | -2.90% | (3) plus a 3.579454 Mhz crystal
; | 1 | 0 | 0 | +4 | 41h | FDh | 110 | 1 | 253 | 110.10 | 0.09% | (4) for a 1.789727 Mhz internal CLK
; | 1 | 0 | 1 | +5 | 40h | 16h | 2400 | 0 | 22 | 2431.69 | 1.32% |
; | 1 | 1 | 0 | +6 | 40h | B9h | 300 | 0 | 185 | 300.69 | 0.23% | 50 baud replaced with 110 baud
; | 1 | 1 | 1 | +7 | 40h | 05h | 9600 | 0 | 5 | 9321.49 | -2.90% |
; |____|____|____|________|_______|________|______|____|_____|__________|________|
;SCTL1 values: +0 +1 +2 +3 +4 +5 +6 +7 ; (1) 70x2 & 70Cx2 with (Baud Table #07)
SCT1TB BYTE >FF,>40,>41,>40,>41,>40,>40,>40 ; (2) divide-by-2 CLK option
;T3DATA values: +0 +1 +2 +3 +4 +5 +6 +7 ; (3) plus a 3.579454 Mhz crystal
T3DATA BYTE >FF,>2E,>FD,>0B,>FD,>16,>B9,>05 ; (4) for a 1.789727 Mhz internal CLK
[Updated on: Thu, 23 May 2024 07:11] Report message to a moderator |
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| Re: DAISY256 works [message #10739 is a reply to message #10738] |
Mon, 29 April 2024 15:09 |
jayindallas
Messages: 110
Registered: June 2021
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Senior Member |
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Bill, aka Plasmo wrote:
"...Are there reasons to use TMS70xx processor? It seems to me Z80 can do the job adequately..."
Your suggestion that a Z80 could do this is certainly true... You can do this with ANY processor, or even a RPi Pico or Zero.
There are no limits for any design anyone wants to create.
The 7000 series make it a little closer to original-art. But reasons you asked about, are in the following:
Radio Shack's Two-Chip, Text-to-Speech & Voice Synthesizer
- - - - - - - - - - - - - - - - - - - - - -
Archer Catalog # 276-1786 . . . $16.95
CTS256A-AL2
Text-To-Speech Controller Chip
Companion to SP0256-AL2 Voice Synthesizer
- - - - - - - - - - - - - - - - - - - - - -
Archer Catalog # 276-1784 . . . $12.95
SP9256-AL2
Voice Synthesizer IC
Allophone Speech Set
- - - - - - - - - - - - - - - - - - - - - -
The original General Instrument CTS256A-AL2 Text-To-Speech Controller Chip, that Radio Shack/Archer later sold in their stores, was actually a PIC7041 microprocessor. The PIC7041 was a second source microprocessor for the Texas Instrument TMS7041. Someone a few years back read the internal ROM of the CTS256A-AL2 and published it on GITHUB and some new work he did on it. Various legacy projects on the CTS and associated SP0256-AL2 Voice Synthesizer IC, makes it easy to grab old, original code with no modifications for 70x1s in external EPROM mode, few modifications for 70x2s (same mode) and more modifications for a 70Cx2 (same mode) or 77C42 with windowed EPROM instead of internal masked ROM.
Instead of being unobtainium micros, Andrew J. Lynch realized that the 7000 Family could utilize external EPROM (mode option) and led that keen observation with his research.
That is why the TMS/PIC 7041 is the focus instead of other possibilities.
Advantages:
(1) You have the original PIC7041 code (was masked ROM in the CTS256A-AL2).
(2) You can add an external EPROM on a new PCB and use cheaper vintage surplus 7041s, or likely parallel interface mode only with 7001s.
(3) With few modifications to the original code, you can run EPROM for NMOS 7042s, likely parallel interface with 7002s.
(4) With more modifications, you can run EPROM for CMOS 70C42, and likely parallel interface with 70C02s.
(5) Even a TMS77C82 or TMS77C42 windowed EPROM processor.
Lots of options, very little new code changes.
[Updated on: Thu, 02 May 2024 11:30] Report message to a moderator |
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| Re: DAISY256 works [message #10741 is a reply to message #10740] |
Tue, 30 April 2024 04:44 |
lynchaj
Messages: 1080
Registered: June 2016
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Senior Member |
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Hi Bill
Yes, there are two separate things happening at once. First, is the CTS256 replacement with common off-the-shelf parts (TMS7001 + 2732) to solve the limited availability of CTS256 chips. That's already done with DAISY256 and all that's left is writing custom firmware to support more TMS7xxx type chips.
Second in the modification to SP0256 to use external ROM and re-utilize non-AL2 SP0256s in a speech synthesis roll like the Radio Shack Text-to-speech circuit. That's where the CPLD project comes in.
I agree that you don't necessarily need a CTS256 or TMS7001 type processor to drive the SP0256. There are RC2014 board with only the SP0256 chip driven by the Z80 (or whatever) processor.
However, if you use the bare SP0256, the host processor has to drive it using the 59 allophones not regular English text. The CTS256 employs the Naval Research Lab text-to-speech algorithm so you can feed it regular English text over the serial port and it drives the SP0256. Or if you want, you can re-implement the NRL TTS algorithm on any other CPU and drive the SP0256 directly.
What I'd like to do with the SP0256 is get a CPLD to interface it to a parallel EPROM like 2732. Then push the SP0256 into one of its test modes and force it to use the external serial ROM instead of its internal mask ROM. Then all those re-marked fake non-AL2 SP0256 chips can now be used to do speech synthesis like the SP0256A-AL2. This should dramatically increase the supply of usable SP0256 chips so people can do Radio Shack style TTS projects without getting fleeced on eBay buying parts (and hoping they are not fake).
Thanks, Andrew Lynch
PS, I think you're CPLD protoboard should work just fine. Assuming it has enough space for a SP0256 circuit with audio amplifier (LM386) plus 2732. It should work fine and just drive it using the Z80 like Scott Baker does with the RC2014 SP0256 board. As I recall, it is just sending a number to the SP0256 using an IO port to get it to speak an allophone. I wouldn't want to write a sentence that way but certainly enough to show the SP0256 is working.
https://www.youtube.com/watch?v=nAmyPuC4WSk
[Updated on: Tue, 30 April 2024 04:56] Report message to a moderator |
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| Re: DAISY256 works [message #10765 is a reply to message #10764] |
Wed, 15 May 2024 03:38 |
lynchaj
Messages: 1080
Registered: June 2016
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Senior Member |
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berzerkula wrote on Wed, 15 May 2024 01:37Hello Andrew,
I do have the Talker PCB and Scott Baker's PCB, is the Daisy256 much different from them? If you desire, I could work with your Daisy256 design if it is quite different.
-William
Hi
The purpose of DAISY256 is/was to test my theory that you could replace the CTS256 with a TMS7001/TMS7041/PIC7001/PIC7041 and an external 2732 EPROM. That turned out to be true, so I think the board was a success. It is based on the mecparts Talker (roughly) with my modifications to for the CTS256 replacement.
You could use DAISY256 as a regular CTS256/SP0256 Radio Shack text-to-speech board and it certainly works fine in that role. Really the only major differences from the Scott Baker PCB and/or mecparts Talker is the extra components for the TMS7001 support.
CTS256 costs $100 plus on eBay if you can find one. A TMS7001 is like $5-$10 and will do nearly the same thing.
If you would like a DAISY256 board, I have some extras and you can have one. I'll ship it to you assuming you are in the US. International shipping has gotten very expensive lately, so I won't be doing that until the rates come back down.
I am planning a second version of DAISY256 but this time will include circuitry to allow usage of non-AL2 SP0256 chips. It should greatly increase the supply of usable SP0256 type chips available. Many (not all) of the fake SP0256A-AL2s are actually remarked SP0256A-xxx for dedicated applications. They'll sort of work but not like you would expect. With the new configuration, I am hoping to disable the internal mask ROM and use an external EPROM instead for the 59 allophone information.
Thanks, Andrew Lynch
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| Re: DAISY256 works [message #10794 is a reply to message #10737] |
Sun, 16 June 2024 11:21 |
lynchaj
Messages: 1080
Registered: June 2016
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Senior Member |
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lynchaj wrote on Mon, 29 April 2024 07:16Hi Jay
Yes, if we could get the TMS70C02 to work with some custom CTS256 firmware that would solve the limited availability of hardware issue. TMS70C02 are really common and inexpensive.
TMS7001, TMS7041, PIC7001, PIC7041, I think they all work fine but aren't nearly as common as TMS70C02. I think TMS77C82 would be even better yet although would require more extensive changes.
Thanks, Andrew Lynch
Hi
Thanks to some help from Fred, I have CTS256A custom firmware for the TMS70C02 with 5 MHz crystal (important, the default 10 MHz crystal will not work!
With this custom firmware, the DAISY256 can use a TMS70C02 to receive serial text and speak just like a CTS256A
Thanks, Andrew Lynch
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| Re: DAISY256 works [message #10823 is a reply to message #10794] |
Mon, 15 July 2024 23:57 |
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berzerkula
Messages: 21
Registered: May 2020
Location: Arkansas, USA
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Junior Member |
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There is a book which may help us, and it has a diagram 1.10
Designing With Speech Processing Chips book by Ricardo Jiménez. He did reference Microchip publication DS5007A-1 1984 but can't find that document anywhere.
-
Attachment: image.png
(Size: 94.12KB, Downloaded 51 times)
You feel a whole lot more like you do now than you did when you used to.
[Updated on: Wed, 17 July 2024 07:11] Report message to a moderator |
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| Re: DAISY256 works [message #10855 is a reply to message #10828] |
Tue, 26 November 2024 17:17 |
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berzerkula
Messages: 21
Registered: May 2020
Location: Arkansas, USA
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Junior Member |
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Unsure if there is still interest in this project, but here is some info that may help us with creating our own exception ROM's.
https://github.com/mecparts/CTS256-exceptions
I never was able to find the document discussed, but I'm glad they found some form of a document and then were able to disassemble the machine code.
However, if the document they mention is the Application Note AN-0505 Revision D, then it does give some info about the exception and user ROM's.
Right now, I'm using Scott Baker's board, which I assembled a few years ago, and have recreated the exception hex and wrote the ROM to an M2732AF1 200nS EPROM.
I used a jumper at 74138 Y4 for address $4000. The system uses the exception ROM.
While playing the Daisy song, some words popped out, which needed some work. I worked out the allophones required to make them sound correct. They still may need some tweaking.
Also some when saying phrases for time like quarter. Some numbers may need some help.
<[BICYCLE]<=[BB2 AA AY SS SS IH IH PA3 KK1 EL] ; BICYCLE
<[CARRIAGE]=[KK1 EH XR EY PA2 JH] ; CARRIAGE
<[FLOWER]<=[FF LL AW ER1] ; FLOWER
<[HEART]<=[HH2 AR TT2] ; HEART
<[MARRIAGE]<=[MM EH XR EY PA2 JH] ; MARRIAGE
<[PEDALING]<=[PP EH EH PA2 DD2 EL IH NG] ; PEDALING
<[POLICEMAN]<=[PP AX AX LL IY SS PA1 MM EH EH NN1] ; POLICEMAN
<[QUARTER]<=[KK3 WW OR PA2 TT2 ER1] ; QUARTER
<[SOMETIMES]<=[SS SS AX AX PA2 MM TT2 AA AY MM ZZ] ; SOMETIMES
I found a document titled "pl02_56_release_notes.pdf" which gives some great knowledge about allophone speech synthesis. It gives good information of which allophones to use in many situations.
This in conjunction with the Emulator at https://github.com/GmEsoft/SP0256_CTS256A-AL2 helps me test before writing the EPROM.
-William
You feel a whole lot more like you do now than you did when you used to.
[Updated on: Wed, 27 November 2024 17:44] Report message to a moderator |
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