Home » RBC Forums » General Discussion » HP2100A, maybe, no a PDP-8 first ! (Thoughts and more on building one from scratch)
| HP2100A, maybe, no a PDP-8 first ! [message #10232] |
Sat, 04 February 2023 23:54  |
ale500
Messages: 44
Registered: April 2018
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I love most things HP, I mean the old HP, the one that produced the HP-67, and the 71 and the 85 and the 2100. Never used one, too young for that but I remember visiting the HP repair office as a teenager and being impressed by all the instruments and the people there.
I want a TTL computer. A FPGA, I feel, is kind of a fake, I do not know why I feel that way, but useful none-the-less.
There are schematics for several old minis like the PDP-8 (would also like one of this), 11 (I'd love one of those), and the HP 2114, 5, 6 and 2100A.
For the ones that (like I) didn't know the HP2100A (and the others 2144..6), it was a microcoded evolution of the 2116, the first HP computer developed on the last second of the 60s. It is a 16 bit machine with few registers and core memory. Extensive documentation exists on how it works and on many of the options and extension cards. This machine was developed to automate test procedures. Nowadays automated test procedures follow similar methods with different hardware.
Of course I printed out the schematics of the HP2100A, pasted the pages together, some are 3 pages long and starting writing VHDL of the schematic, realizing soon enough that the bidirectional buses (plenty of those) were going to make the effort more painful.
At this point I said to myself, eee, no, this is not the way to go, how about RTFM !  . I do not understand how this thing works. I have to understand. I decided to write a VHDL behavioral model of the CPU, without microcode, hardwired. After a couple weeks I have a model that passes memory, alter skip and shift rotate tests. The IO is kind of faked and allows for minimal "operator console" interaction. Because this computer has blinken lights ! .
I'd really want to do this machine in TTL but only in like 2 boards, the 2100 has microcode, the earlier ones are hardwired (even more logic). Examining the schematics shows the mixture of TTL and CTL logic. CTL logic is used to interface the boards together (you need like 10 boards for a CPU with memory) and to produce AND-OR logic. These CTL gates are power hungry, need like 200 mW per package. No idea if such chips are available, not that I want to use those in this project.
My idea would be to approach the thing a bit differently, do a RTL model of the 2100A with microcode, kind of fateful to the schematics in a bid to "reduce" and understand the logic, now that I have a working VHDL model to compare to. Later I'll see how to map that to TTL logic. The CTL logic is kind of everywhere but maybe one could replace it with GALs because they build AND-OR chains, but without going over the board though (FPGA). And yes, my VHDL model runs on a FPGA, a puny MachXO2, it needs like 786 out of 2112 LUTs (MachXO2-2000) with 4 kWords of memory.
I'll upload my code to github.
My choice of TTL would be to try as much as possible in HC or HCT, the 74181s where done in TTL, Shottky, LS and I think ALS and F. But no HC or similar. I have some 74LS/S181s, and got some skinny (like the 74F181) 181s from aliexpress, most probably fakes. Some HCTs from aliexpress are also either LS or similar (got a bunch of 74LS245, they eat like 50 mA per package).
A good place to start is here: https://bitsavers.org/pdf/hp/21xx/02100-90159_2100cpuCourse. pdf as it describes quite in detail the whys and the hows.
Note: There is this project: https://hackaday.io/project/184695-pdp-1170-replica
He is re-building the 11/70 boards, he got himself a data path board. The 11/70 has many boards. But it is a powerful machine.
[Updated on: Sat, 18 March 2023 04:22] Report message to a moderator |
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| Re: HP2100A, maybe [message #10282 is a reply to message #10232] |
Sat, 18 March 2023 02:31  |
ale500
Messages: 44
Registered: April 2018
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Kind of halfway through doing the VHDL behavioral model of the 2100 CPU I thought that the PDP-8 had a similar instruction set. Then I looked into it and saw that that was indeed the case.
I grabbed the schematics of the PDP-8A, read a bit the documentation and decided to do a PDP-8 as aside project. Using the methodology I employed with the 2100, I started doing a behavioral model and some other models to try to find a useful compromise between number of TTL chips and easy of implentation.
Here you can see my current efforts: https://github.com/raps500/ALEPDP8
The current variant, called T4, is the one that I'm working on: a partial schematic, the one I'm using now to build a breadboard version can be opened with KiCad 6.
I have been considering different possibility, mainly for the data path:
The arithmetic/logic operations needed are: add, and, or, complement.
One of them uses 3 '194 as accumulator. These shift registers enable left/right shift or load, solving the RAL/RAR, CLA opcodes. The ISZ opcode needs the adder too but the other adder path has to be 0, meaning that the outputs of the '194s need a buffer like the '367 to force a 0 there. The PC can be realized with a trio of '193s up/down counters.
Another approach, the one I'm using now, has a trio of '670 as "register file" containing both the AC and PC. A trio of '194s provides shifting and latching of ALU results. 3 '181s provide for all arithmetic/logic operations except shifts.
Have fun !
[Updated on: Sat, 18 March 2023 04:20] Report message to a moderator |
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