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| Re: Design help [message #10212 is a reply to message #10210] |
Fri, 27 January 2023 08:09   |
jayindallas
Messages: 110
Registered: June 2021
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Senior Member |
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The original circuit relied on any AND output being HIGH/TRUE to make the final output HIGH/TRUE.
The 74'09 AND.OC is not the right chip for the right-hand circuit.
The 7409 will only create an active wired-or output when its AND output is LOW/FALSE.
You could think of the 7409.OC as being used when all GO statuses must generate a HIGH/TRUE, but ABORTS with a LOW/FALSE when any condition is NOT true.
"...Houston... We have a problem..."
If you use 74'01 NAND.OC that will get wired-or LOW/TRUE where the original AND inputs generated a HIGH/TRUE.
The 6 decision logic is now correct but the output is open collector LOW/TRUE.
Just add one of your extra inverters to turn the LOW/TRUE into a HIGH/TRUE.
Original Equation:
___ ___ ___ ___ ___
(IEI x nM1)+(INT x nM1)+(nCS x nM1)+(nIORQ)+(nRD x nM1)+(nRD x nM1)
(AND) OR (AND) OR (AND) OR OR (AND) OR (AND)
[Updated on: Fri, 27 January 2023 14:26] Report message to a moderator |
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| Re: Design help [message #10240 is a reply to message #10213] |
Sat, 11 February 2023 07:36 |
jayindallas
Messages: 110
Registered: June 2021
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Senior Member |
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Nice circuit and faster. Looks like a CPLD construct 'gone retro'. 
I think there is also a 7403 which is another NAND.OC with a different pinout, though I didn't check to see if that was available at Mouser.com. I only looked at the system boundary of the circuit in the first posting, I didn't go back deeper into the Z80 signaling.
[Updated on: Fri, 24 February 2023 19:45] Report message to a moderator |
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