Home » RBC Forums » General Discussion » Generic RetroComputer project (Z80, 6502, 8085, 6809, 68008, 32008, oh my!)
| Generic RetroComputer project [message #9772] |
Wed, 23 February 2022 07:10  |
plasmo
Messages: 916
Registered: March 2017
Location: New Mexico, USA
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Senior Member |
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I'm thinking about a low-cost and modular processor-agnostic platform to explore 5V processors of 1970's and 1980's. The thoughts revolve around the idea of different retro processor boards but reuse memory and peripherals; I want these computers to be standalone, i.e., with its own keyboard and monitor; and finally, for once in my life, I'm going to put it in a box!
This is the features of Generic RetroComputer project:
* 5V 8-bit processors and some 5V 16-bit processors
* Reuse memory and peripherals
* Standalone computer
* Low cost
* Design for PacTec CM5-200 enclosure
Not a lot of specifics because different processor family have different end points. For Z80, ROMWBW is the goal; for 6502, it is DOS/65; for 8085, it is CP/M; for 68008, it is CP/M68K (lame! there must be a better goal!); for 6809 and NS32008, I don't know. For now I'll avoid processors that need multiple voltages like 8080.
It is obvious from the set of features that the design has a backplane for various boards to plug in. Low cost drives the pc board to no bigger than 100x100mm which is the backplane size. The PacTec CM5-200 enclosure means the board dimension is 1.6" tall by 4" wide. Boards of such dimension can step-and-repeat 3 times to fit in a 4"x4" panel, another cost-saving feature. There must be a backplane signal definition that can accommodate different processor families and there must be a programmable hardware to reuse the signals and adjust timings for different processors.
I've designed a few rev0 boards to explore the concept and I'm encouraged by the results. So I'm starting a design blog to document my journey in Generic RetroComputer. This is an ambitious project and I expect it to last several years so periodically I'll edit this first post for updated table of contents and progress report.
Bill
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| Re: Generic RetroComputer project [message #9775 is a reply to message #9774] |
Wed, 23 February 2022 12:38  |
plasmo
Messages: 916
Registered: March 2017
Location: New Mexico, USA
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The retro components are used components and many (possibly most) are re-labelled parts, so the the concerns about inadvertently destroying rest of the computers with unknown CPU is a valid one. Buffering may be a solution, but it is also a question of the cost of insurance vs insured. By reducing the board count to minimum when new or unknown processor is added, the number of boards at risk is minimized. Because each board is simple and inexpensive, even if a few was destroyed, they can be built back up easily and inexpensively. The current design needs one board, the CPLD board, to test out a new, unknown processor. The CPLD is Altera EPM7128S equivalent to the $10 (Mouser) Atmel ATF1508, but used Altera CPLD is about 1/3 the price of new ATF1508, so the cost of risk taking is not much. The next board that's added to a new unknown processor is RAM/Flash board which is more expensive, about $8 for SST39SF040 + AS6C4008, but the new unknown processor has already been checkout with CPLD board, so risk to RAM+ROM is pretty low. After RAM/ROM, the risks to subsequent boards are insignificant.
In term of signal integrity, 4"x4" backplane is quite small so I expect CMOS processors to have sufficient drives. The NMOS processors potentially will have more problems; I don't know, I guess I'll find out soon enough.
Thanks for your feedback.
Bill
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| Re: Generic RetroComputer project [message #9779 is a reply to message #9775] |
Thu, 24 February 2022 08:22 |
plasmo
Messages: 916
Registered: March 2017
Location: New Mexico, USA
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Senior Member |
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GRC Backplane
The Generic RetroComputer's backplane is a 4"x4" pc board with passive components comprise of six 2x25 female sockets, a 44-pin IDE connector, power jack, and reset button. Its mounting holes are designed for PacTec's CM5-200 enclosure.
Here are the signal definitions for the 2x25 female connectors.
* 16 addresses for 64KB memory space
* 4 banks to expand addressing up to 512KB
* 8 data
* 8 CPU controls where write strobe, interrupt, non-maskable interrupt, and wait state are assigned; other 4 controls are assigned based on processor family in use.
* Dedicated chip select for RAM.
* Dedicated chip select, write strobe, and read strobe for IDE device
* 5 general purpose chip selects.
[Updated on: Thu, 24 February 2022 08:25] Report message to a moderator |
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| Re: Generic RetroComputer project [message #9784 is a reply to message #9782] |
Fri, 25 February 2022 06:38 |
plasmo
Messages: 916
Registered: March 2017
Location: New Mexico, USA
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Senior Member |
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CPLD Board
GRC bus is a "decoded bus" (please help me with a better term) where different processor-specific control signals are decoded into standard enable signals for the common memories and peripherals. The translation of different processor-specific signals into standard control signals is done in the CPLD board. The CPLD is user-programmable to handle different processors; it does not need to be complex, but needs sufficient I/O pins to receive and generate the many signals from the backplane. One 44-pin CPLD is not enough, but two CPLD in hobbyist friendly PLCC44 package may handle all the I/O. For greater flexibility I I picked the EPM7128S in 100-pin SMT package (I happened to have lots of it) to help me with the development of GRC concept. For hobbyist friendly design, dual 44-pin CPLD in through-hole sockets is the targeted final CPLD board.
Address decode and bank switching are trivial applications of CPLD, hardly use any macrocell resources. Since I am using a 128-macrocell CPLD for conceptual development, I will incorporate a serial port, small boot ROM, and diagnostic functions. The CPLD can be reprogrammed many times (datasheet says 100 times, minimum) for debugging unknown processors and new peripherals. In next posting I'll demonstrate how the CPLD board is used to test Z80 and 6502 processors and every subsequent new processors.
Bill
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| Re: Generic RetroComputer project [message #9797 is a reply to message #9787] |
Mon, 28 February 2022 07:25 |
plasmo
Messages: 916
Registered: March 2017
Location: New Mexico, USA
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Senior Member |
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CPLD Tester for Z80
A generic tester for retro CPU is useful because most old CPU are used parts and many are re-labelled. The used markets like eBay, Aliexpress have excellent return policy but parts need to be tested timely to be covered by the return policy. Before inserting an unknown CPU into a full-up system, it is a good idea to check it out with minimal hardware.
The NOP test mentioned previously tests only one instruction and requires a scope to observe test outputs. Nevertheless it is a fair test to establish the part is at least the right CPU and will power up. This post describes a generic CPLD tester for CPU that can exercise more instructions and display output on terminal emulator. No tester can cover 100% of faults, but this test should provide sufficient confidence in the targeted CPU to install it in a full-up system.
This tester is based on the CPLD board. It consists of two major components; a small lookup table that serves as boot ROM, and a serial transmitter.
Verilog (and VHDL as well) has a construct for lookup table where multi-bit inputs are translated to multi-bit outputs. By assigning the inputs as addresses and outputs as 8-bit data, the lookup table may serve as a ROM. Unlike ROM, the translation are done with combinatorial logic so it take very little macrocell resources to implement a small ROM in CPLD.
Here is a small ROM program in Z80 assembly:
A 1 ;embedded ROM code in CPLD
A 2 ;keep it simple
A 3 ;no RAM, so no subroutine calls
000000F8 A 4 TX equ 0f8h
A 5 org 0
00000000 A 6 start:
00000000 D3 F8 A 7 out (TX),a
00000002 A 8 delay:
00000002 04 A 9 inc b
00000003 20 FD A 10 jr nz,delay
00000005 0C A 11 inc c
00000006 20 FA A 12 jr nz,delay
00000008 3C A 13 inc a
00000009 C3 00 00 A 14 jp start
This simple program output a byte to serial port, wait a while, increment the byte and output it again and again. This is the same program in Verilog lookup table:
module Z80ROM(
input [3:0]addr,
output reg [7:0]ROMdata);
always @(*)
begin
//embedded Z80 instruction in ROM
case(addr)
4'b0000: ROMdata = 8'hd3; //out(TX),a
4'b0001: ROMdata = 8'hf8;
4'b0010: ROMdata = 8'h04; //inc b
4'b0011: ROMdata = 8'h20; //jr nz,delay
4'b0100: ROMdata = 8'hfd; //
4'b0101: ROMdata = 8'h0c; //inc c
4'b0110: ROMdata = 8'h20; //jr nz,delay
4'b0111: ROMdata = 8'hfa; //
4'b1000: ROMdata = 8'h3c; //inc a
4'b1001: ROMdata = 8'hc3; //jp start
4'b1010: ROMdata = 8'h00; //
4'b1011: ROMdata = 8'h00; //
4'b1100: ROMdata = 8'h00; //
4'b1101: ROMdata = 8'h00; //
4'b1110: ROMdata = 8'h00; //
4'b1111: ROMdata = 8'h00; //
endcase
end
endmodule
The program expects a serial transmitter at I/O address 0xf8, so we'll reuse a parallel-in serial out shift register (74165) from Quartus TTL library and modify the front end to generate START bit. A baud rate generator and decode for I/O address 0xf8 are also added. Please refer to the CPLD schematic below.
With Z80 board and CPLD board populated on the GRC backplane, this is the output displayed on TeraTerm serial terminal emulator.
[Updated on: Mon, 28 February 2022 07:29] Report message to a moderator |
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| Re: Generic RetroComputer project [message #9803 is a reply to message #9797] |
Wed, 02 March 2022 20:44 |
plasmo
Messages: 916
Registered: March 2017
Location: New Mexico, USA
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Senior Member |
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6502 Board
While waiting for RAM/ROM pc board from JLCPCB, I assembled a 6502 CPU board.
Like the Z80 board, it is a simple board with most signals go directly to GRC bus. The four CPU specific signals are not assigned at all because 6502 is a very simple CPU with no I/O space and uses high phase of clock (PHI2) to indicate valid addresses and data. The maximum clock for W65C02 is 14MHz but because the flash access time of 70nS, the nominal clock is 7.37MHz. The schematic for the 6502 is attached below.
Like Z80, I also constructed a "NOP" test plug; 6502 NOP instruction is 0xEA. Because NOP instruction is executed in 2 clocks, 6502's A15 also rolls over every 17.8mS, same timing as Z80 even though 6502 clock is half of Z80 clock.
CPLD tester for 6502
CPLD tester for 6502 is very similar to that of Z80. 6502 has no separate I/O space so transmitter is assigned to memory location $E400. The following is the ROM program in 6502 assembly for putting incrementing characters out to serial port. It is the same idea: wait a while, put out a byte to serial transmitter, increment the byte, repeat.
000000r 1 ;Transmit incrementing data to serial port
000000r 1 .pc02
000000r 1 .org $fff0
00FFF0 1 start:
00FFF0 1 CA DEX ;16-bit delay
00FFF1 1 D0 FD BNE start
00FFF3 1 88 DEY
00FFF4 1 D0 FA BNE start
00FFF6 1 8D 00 E4 STA $e400 ;write to transmitter
00FFF9 1 1A INC
00FFFA 1 80 F4 BRA start
00FFFC 1 F0 FF .word start
The corresponding Verilog Lookup table:
module CPLD_ROM(
input [3:0]A,
output reg [7:0]Dout);
always @(*)
begin
//Boot ROM in CPLD
case(A)
4'b0000: Dout = 8'hCA; // DEX
4'b0001: Dout = 8'hD0; // BNE
4'b0010: Dout = 8'hFD; //
4'b0011: Dout = 8'h88; // DEY
4'b0100: Dout = 8'hD0; // BNE
4'b0101: Dout = 8'hFA; //
4'b0110: Dout = 8'h8D; // STA
4'b0111: Dout = 8'h00; //
4'b1000: Dout = 8'hE4; //
4'b1001: Dout = 8'h1A; // INC
4'b1010: Dout = 8'h80; // BRA
4'b1011: Dout = 8'hF4; //
4'b1100: Dout = 8'hF0; //
4'b1101: Dout = 8'hFF; //
4'b1110: Dout = 8'h00; //
4'b1111: Dout = 8'h00; //
endcase
end
endmodule
The serial output to TeraTerm terminal emulator looks exactly like Z80's
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| Re: Generic RetroComputer project [message #9813 is a reply to message #9809] |
Wed, 09 March 2022 18:14 |
plasmo
Messages: 916
Registered: March 2017
Location: New Mexico, USA
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Senior Member |
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I made two versions of GRC backplane, one for compact flash and another for disk-on-module. Electrically they are the same but mechanically the 44-pin connector is mirrored between CF and DOM. Furthermore, CF adapter is taller so it won't fit the PacTec CM5-200 enclosure without a slot cutout on top of the box. I like DOM better but because DOM reader is not easy to find, it is necessary to transfer files serially from PC to DOM whereas CF disk image can be transferred using tools like Win32diskimager. Cost wise there are no real difference; used 128MB DOM is about $5; used CF disk is $2 plus $5 for CF adapter. Pictures of GRC with CF disk, GRC with DOM, and GRC with DOM fitted inside CM5-200 enclosure.
Bill
----------------Additional Info 3/12/22
Compact Flash and Disk-on-module decoding logic are the same. It is quite simple as shown in schematic below. The I/O addresses are 0x10 to 0x17 so it will be automatically recognized by ROMWBW. It is important to delay read and write strobes by one clock from the assertion of the chip select. Some brands of CF disks will work without the delay, but other brands may not. This is a common fault with many current CF board designs.
The DOM is recognized by ROMWBW. Nominal power consumption for the system, DOM, Z80@14.7MHz, CPLD, RAM/ROM512K, is 140mA@5V.
[Updated on: Sat, 12 March 2022 10:17] Report message to a moderator |
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| Re: Generic RetroComputer project [message #9817 is a reply to message #9815] |
Mon, 14 March 2022 07:47 |
plasmo
Messages: 916
Registered: March 2017
Location: New Mexico, USA
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Senior Member |
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GRC Quad Serial board
I have a large number of OX16C954 in QFP-100 on hand so it is the logical device for multi-channel serial board. The simple serial port in CPLD is useful for bringing up new system but have served its purpose. it is being replaced with the OX16C954 based multi-channel serial board and CPLD's resources can be reused to develop other capabilities.
OX16C954 is designed for Motorola or Intel bus interface which is ideal for GRC that hosts both Motorola and Intel style retro processors. The picture shows the block of 8 jumpers in "Up" position which is the Intel bus interface. With Motorola bus interface the block of jumpers are placed in "Down" position. GRC requires 32 bytes of contiguous I/O or memory locations; nCS2 generated by CPLD is the base address chip select. To be compatible with ROMWBW, the default Z80 I/O addresses are 0xC0-0xDF. OX16C954 is very capable and very fast; it has 128-byte deep transmit and receive FIFO; and it can handle clock up to 60MHz. For GRC-Z80, the clock is same as Z80 CPU or 14.7456MHz. Schematic of GRC Quad Serial board is attached.
To generate ROMWBW ROM that detects the quad serial board and set appropriate baud rate I added this two lines to configuration file:
UART4 .SET TRUE ; UART: AUTO-DETECT 4UART UART
UARTOSC .SET 3686400 ;clock source is 14.7MHz
This is ROMWBW booting up, found GRC quad serial board, and use UART0 as the console.
RomWBW HBIOS v3.1.1-pre.148, 2022-03-12
RC2014 Z80 @ 14.745MHz
0 MEM W/S, 1 I/O W/S, INT MODE 1, SBC MMU
512KB ROM, 512KB RAM
ROM VERIFY: 00 00 00 00 PASS
AY: MODE=RCZ80 IO=0xD8 NOT PRESENT
UART0: IO=0xC0 16650 MODE=115200,8,N,1 FIFO AFC
UART1: IO=0xC8 16650 MODE=115200,8,N,1 FIFO AFC
UART2: IO=0xD0 16650 MODE=115200,8,N,1 FIFO AFC
UART3: IO=0xD8 16650 MODE=115200,8,N,1 FIFO AFC
ACIA0: IO=0x80 ACIA MODE=115200,8,N,1
DSRTC: MODE=STD IO=0xC0 NOT PRESENT
MD: UNITS=2 ROMDISK=384KB RAMDISK=256KB
FD: MODE=RCWDC IO=0x50 NOT PRESENT
IDE: IO=0x10 MODE=RC
IDE0: 8-BIT LBA BLOCKS=0x0003E800 SIZE=125MB
IDE1: NO MEDIA
PPIDE: IO=0x20 PPI NOT PRESENT
Unit Device Type Capacity/Mode
---------- ---------- ---------------- --------------------
Char 0 UART0: RS-232 115200,8,N,1
Char 1 UART1: RS-232 115200,8,N,1
Char 2 UART2: RS-232 115200,8,N,1
Char 3 UART3: RS-232 115200,8,N,1
Char 4 ACIA0: RS-232 115200,8,N,1
Disk 0 MD0: RAM Disk 256KB,LBA
Disk 1 MD1: ROM Disk 384KB,LBA
Disk 2 IDE0: Hard Disk 125MB,LBA
Disk 3 IDE1: Hard Disk --
It is not all working correctly, however. There are two problems so far:
1. Quad serial board is detected and boot MOST of the times but not every time.
2. As the console port it echos back characters twice (yes, I make sure local echo is disabled).
I'm investigating...
Bill
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| Re: Generic RetroComputer project [message #9830 is a reply to message #9827] |
Mon, 21 March 2022 06:58 |
plasmo
Messages: 916
Registered: March 2017
Location: New Mexico, USA
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Senior Member |
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GRC VGA-PS2 board
The GRC VGA-PS2 board receives inputs from PS2 keyboard and displays 64-col, 48-row text on VGA monitor. GRC becomes a standalone computer with the addition of VGA-PS2 board while retains the ability to communicate/upload/download with the host computer using the Quad Serial board.
The video outputs 8-pixel by 8-pixel monochrome texts as 64 columns by 48 rows display. The display format is 640x480 60Hz VGA with pixel clock of 25.175MHz. All video data (texts & fonts) are contained in a 4KB dual port RAM that's mapped somewhere in the memory space as a 4KB block of write-only memories. I said "somewhere" because I'm still working out the memory map details so not to conflict with ROMWBW's memory utilization. By using dual port RAM, texts and fonts can be updated anytime without causing "snowing" effects. Texts are in the first 3K of the dual-port RAM while fonts are in the last 1K of the DPRAM. Z80 has large 64K I/O space so it is possible to place the 4K dual port RAM in Z80's I/O space but I chose memory mapped scheme because I want to use the same board for Z80 as well as memory-mapped processors like 6502 and 68008.
VGA controller is a modest 64-macrocell CPLD, EPM7064S, that continuously reads text data from second port of DPRAM, looks up the associated fonts and drives the pixel output at 25.175MHz rate. The VGA controller runs independently in the background invisible to the processor; it has no control/status register and generates no interrupt.
PS2 controller is a dedicated CPLD state machine for PS2 keyboard. It polls the PS2 keyboard for available input, serially clocks in data, checks parity, and stores data in a hold register while keeping keyboard from sending more data until the current data in the hold register is read out. PS2 controller has status register but generates no interrupt.
Attached is the schematic of VGA-PS2 board. It is quite dense so it is implemented as 4-layer pc board.
Bill
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| Re: Generic RetroComputer project [message #9840 is a reply to message #9833] |
Tue, 29 March 2022 17:23 |
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Wayne W
Messages: 385
Registered: October 2015
Location: Fallbrook, California, US...
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Senior Member |
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plasmo wrote on Tue, 22 March 2022 07:30Wayne,
My original though was to place the VGA RAM at the top of RAM disk and reduce the RAM disk's Disk Parameter Block by 4K but finding a 4K block in HBIOS is a better solution. I'm not concerned about compatibility across different processor families; different processors will need different CPLD designs so memory map of VGA RAM can be changed as well. It is also possible to make the VGA RAM relocatable with the addition of a hardware configuration register in CPLD.
Hi Bill,
Sorry, just saw this message. I'm bad at monitoring this forum since it doesn't send emails yet.
So, yes, if you can map the display buffer to the top 4K of the HBIOS bank, that would probably be ideal. Note that the HBIOS bank is dependent on the size of RAM. Essentially, it is located at MAX BANK - 2. So, in this case it will be bank D.
Thanks,
Wayne
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| Re: Generic RetroComputer project [message #10301 is a reply to message #10296] |
Sat, 01 April 2023 07:34 |
plasmo
Messages: 916
Registered: March 2017
Location: New Mexico, USA
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Senior Member |
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I now have a monitor software for GRC that can take input from either TeraTerm serial emulator on the PC or PS2 keyboard attached to GRC's video/keyboard board. The output is displayed on both TeraTerm on the PC and VGA video attached to GRC. So it is now a standalone computer, at least at the monitor level. The output to TeraTerm and VGA video are the same except in the case of display memory. Non-printable characters (0x0-0x1F, 0x80-0xFF) are displayed as dots (.) on TeraTerm but are displayed as the actual data supported by the corresponding fonts. See the screen capture of TeraTerm display vs picture of the VGA monitor. Note data 0x80 and above is displayed as reverse video. This was suggested by etchedpixels so to enable pseudo graphic character set for all possible permutations of 2x4 blocks.
The CPLD on video/keyboard board is not large enough to support hardware scroll so scrolling is done in software but it is fairly fast with 14.7MHz Z80. CPLD does have enough logic for generating 60Hz interrupt synchronous to video's vertical sync. Up to this point no software needed interrupt, including RomWBW, but 60Hz interrupt will provide a sense of elapsed time.
The last step for GRC-Z80 is implement video/keyboard functions for CP/M.
Bill
[Updated on: Sat, 01 April 2023 07:34] Report message to a moderator |
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