Home » RBC Forums » General Discussion » CPLD Trainer with 6502, Z80, and more... (EPM7128SLC84, W65C02, Z80, and other SBC)
| CPLD Trainer with 6502, Z80, and more... [message #9754] |
Fri, 11 February 2022 08:22  |
plasmo
Messages: 889
Registered: March 2017
Location: New Mexico, USA
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I've created a homepage for CPLD Trainer with 6502 here:
https://www.retrobrewcomputers.org/doku.php?id=builderpages: plasmo:6502:cpld6502:cpld6502r0
This is an inexpensive 100mmX100mm 2-layer PCB CPLD trainer in through-hole technology based on Altera EPM7128SLC84. A 6502 processor and associated EPROM and RAM are part of the design. At the bottom of the homepage are 10 training sessions published on 6502.org recently. Topic covered are initial power up, displaying 6-digit 7-segment display, testing 6502 with CPLD, and 6502 SBC. The development phase is completed with Session 10. Future sessions will deal with various projects I like to do with this board. I'm expecting at least 10 more sessions with projects like I2C, SPI, PS2 keyboard, WS2812B driver, EPROM programmer, VGA beam racing, W65C816 option, RC6502 expansion boards, etc.
A similar CPLD + Z80 trainer should be do-able, but one project at a time...
Bill
[Updated on: Thu, 14 April 2022 07:25] Report message to a moderator |
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| Re: CPLD Trainer with 6502 [message #9756 is a reply to message #9755] |
Sat, 12 February 2022 06:50  |
plasmo
Messages: 889
Registered: March 2017
Location: New Mexico, USA
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CPLD resources are limited so I need to be efficient. It is hard for me to work efficiently in verilog anymore except for special cases so I've regressed to schematic. I also code in assembly because I no longer can write efficient C for 8-bit processors with small memory. Retro computing suits my retro mindset.
Bill
[Updated on: Sat, 12 February 2022 06:51] Report message to a moderator |
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| Re: CPLD Trainer with 6502 and Z80 and... [message #9853 is a reply to message #9758] |
Fri, 08 April 2022 06:48 |
plasmo
Messages: 889
Registered: March 2017
Location: New Mexico, USA
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Updated the CPLD trainer to rev1 pc board to correct known pcb errors. I also added a new feature: multiple 40-pin CPU are co-located on the pc board. Because CPLD can be reprogrammed to accommodate different CPU, the same pc board design can accommodate different CPU as long as the CPU is in 40-pin 600-mil DIP package. Each CPU is located in the same board area but offset by 0.1". In theory 6 different CPU can co-located in the same area but rev1 pc board implemented 6502, Z80, and an uncommitted 40-pin DIP which can be any 40-pin CPU with connections manually wired in. This is similar in concept to Generic RetroComputer except it is a single_board-multiple_retrocomputer approach.
By reprogramming the CPLD for Z80 timing, populating the trainer with Z80, 512K RAM, 512K flash and installing ROMWBW software in flash, it boots up and able to run CP/M with 384KB of ROMdisk and 256KB of RAMdisk. This is sufficient to explore CP/M. For more disk space a compact flash board can be added to the expansion bus.
Replace Z80 with W65C02, reprogram the flash, and reprogram the CPLD, it becomes a 6502 SBC.
[Updated on: Fri, 08 April 2022 06:51] Report message to a moderator |
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| Re: CPLD Trainer with 6502 and Z80 and... [message #9868 is a reply to message #9855] |
Thu, 14 April 2022 07:29 |
plasmo
Messages: 889
Registered: March 2017
Location: New Mexico, USA
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The original intent of the PS2 keyboard interface was to build a standalone computer with the addition of a VGA display. That is still the plan but lately I've been exploring PS2 keyboard interface and it seems interesting to have a front panel interface using the keyboard as input and 7-seg display as output. It is like the old fashion front panel where addresses and data can be manually entered and have CPU executes the manually entered code. A dedicated microcontroller probably is the best approach to re-implement the old fashion front panel. The trainer has a modest CPLD but no microcontroller so the following is my attempt to implement the front panel function using CPLD only.
The front panel has two modes of operation, data entry mode and run mode. In data entry mode the processor (Z80 in this case) is in reset, the 7-seg display is under control of the keyboard, and the keyboard shows or modifies memory contents with few simple single-key commands. There are six 7-seg display separated into 4-digit address field and 2-digit data field. The data entry mode commands are:
* Space key reset address field to 0x0
* Enter key writes data on display to current memory location, then reads and displays content of next memory location
* Backspace key decreases current memory location by one, then reads and displays the memory content.
The keys 0-9, a, b, c, d, e, f are hexadecimal input for the 8-bit data field. Following a Enter keystroke, a hex input will modify the most significant nibble; next hex input will modify the least significant nibble; if there are additional hex input the active digit will alternate between the most significant and least significant digit.
The address field is not directly modifiable. Space key reset it to 0x0, Enter key advances the address while Backspace key decreases the address.
* Escape key toggles between data entry mode or run mode. The decimal points of 7-seg display are lit when in data entry mode.
When in run mode the 7-seg display shows the current address generated by the Z80 processor and data value it is reading or writing. The run mode only has two commands:
* "S" key to single step
* "R" key to run continuously. Press "R" again stops the running processor so it can be single stepped.
------------------------------------------------------------ ------
The computer being controlled is quite simple, just a Z80 and a RAM that takes up the entire 64K of Z80's memory space. There is an expansion bus to plug in I/O board such as a serial port.
Picture shows the display in data entry mode (the decimal points are lit) The address field is 0x1C and data value is 0xEF.
It was fun project. I found manual data entry a lot easier than the old toggle-switch front panel of my first computer, Altair 8800. The limitation in manually modifiable address field is not too serious since I'm unlikely to manually enter hundreds of data. Press and hold the Enter key does advance the address field sufficiently fast. Backspace key can quickly correct data entry errors. All in all, I'm pleased with it. I can provide design data if anyone interested in the detail CPLD implementation.
Bill
[Updated on: Thu, 14 April 2022 07:37] Report message to a moderator |
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| Re: CPLD Trainer with 6502, Z80, and more... [message #10010 is a reply to message #10009] |
Sun, 10 July 2022 18:46 |
plasmo
Messages: 889
Registered: March 2017
Location: New Mexico, USA
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I think I'm too ambitious trying to get the front panel function working on a processor I'm not familiar with and on an unproven hardware. It is like fighting wars on three fronts. So I'm abandoning the front panel approach; I'll debug the new 6809 hardware using the traditional way where I burn a small test program in EPROM and see if it runs as expected. This is taking many baby steps that will require many EPROM programming cycles but easier to debug when something didn't work as expected.
So I created a serial port in CPLD and a simple address decode scheme for EPROM and wrote the first test program, "Hello World" that does not need RAM. Only 6809 and EPROM are populated.
;fef9 is serial data reg
;fef8 is serial status reg
FF00 org $ff00
FF00 start
FF00 8EFF17 ldx #signon ;point to sign on message
FF03 chkTxE
FF03 F6FEF8 ldb $fef8 ;check for TxEmpty
FF06 C401 andb #1
FF08 27F9 beq chkTxE
FF0A A680 lda ,x+ ;get a character
FF0C 2706 beq spin ;check for null terminator
FF0E B7FEF9 sta $fef9
FF11 7EFF03 jmp chkTxE ;get more characters
FF14 spin ;stop here
FF14 7EFF14 jmp spin
FF17 signon
FF17 0D0A48656C6C6F20576F726C64210D0A00 fcb $d,$a,"Hello World!",$d,$a,0
FFFE org $fffe
FFFE FF00 fdb start ;reset vector
It actually works!
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| Re: CPLD Trainer with 6502, Z80, and more... [message #10012 is a reply to message #9754] |
Wed, 13 July 2022 14:51 |
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berzerkula
Messages: 17
Registered: May 2020
Location: Arkansas, USA
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 Greetings,
I used OSHPark to fabricate the boards. Parts have been assembled per Session 1 instructions, but I have also installed all the resistors, capacitors, and the SIP sockets for the 6502/Z80, PLCC84, JTAG header, power barrel jack and switch, supervisory IC, the two 7 segment LED's with associated 2N2222A's. I have followed a guide for loading a project, making sure the right device is selected along with the proper programmer for JTAG. Everything looks okay. Now I've attempted with two programmers. One is a Wave Blaster V2 from Waveshare, and another is an Altera USB Blaster (has brown writing for USB BLASTER text) from an Altera box with manual. When I attempt to autodetect with JTAG, the CPLD gets warm, draws about 120mA by itself, then with the programmer attached, gets to about 260mA and then the detection fails with a JTAG chain failure. I have 3 EPM7128SCL84-10N's and I get same results with all 3 CPLD's (New Old Stock at look like it) and either USB Blaster programmer.
My first idea is to build up a 2nd PCB (I have 3), and see if the same problem results but this time only doing the absolute bare minimum, but before assembling, ringing out some traces and making sure there wasn't a fabrication error.
The second idea is to build a very crude circuit with prototyping board and see if I can program it while not using the PCB.
The third way I will be able to attempt Friday, is to use the University board which I'm waiting from UM Columbia to arrive across state lines. I guess the dept didn't want it anymore! (Lucky me).
Any tips in troubleshooting? I'm hoping the CPLD's aren't bad, but the University board has one the same device but at -7N spec.
I've attached the partially assembled board for session 1.
I suspect I've been bit by the same issue mentioned in retro-comp where NOS aren't really NOS and are parts taken from devices where the JTAG interface is disabled. Woe is me, then! In which case, I'll attempt the apply 5V, then 12V with resistor, then attempt to Autodetect and program, then back to 5V and see if it works with these devices.
-William
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Attachment: PCB1.jpg
(Size: 4.73MB, Downloaded 1296 times)
You feel a whole lot more like you do now than you did when you used to.
[Updated on: Thu, 14 July 2022 07:08] Report message to a moderator |
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| Re: CPLD Trainer with 6502, Z80, and more... [message #10013 is a reply to message #10012] |
Wed, 13 July 2022 17:01 |
plasmo
Messages: 889
Registered: March 2017
Location: New Mexico, USA
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William,
Your board looks good. The connection to CPLD is very simple, just the programming header plus two 4.7K resistors associated with pull up & pull down of JTAG signals. There are very little that can go wrong, JTAG programming header is actually 2x5 header, but I have had a large supply of surplus headers with pin 10 missing which is a redundant ground pin. The missing pin 10 helps me identify which way the JTAG programming ribbon should be positioned (ribbon with strip side goes to pin 1). I see you have the same arrangement as well. I think your assessment of used CPLD with locked JTAG is the most likely answer.
Completely unused EPM7128SLC84 from factory should draw very little current (under 5mA). With USB blaster attached it may draw 50mA. 120mA to 260mA is not excessive for programmed CPLD, so it is still possible you have a real EPM7128SLC84.
Since you live in the States, I'll propose a swap: two of my proven EPM7128SLC84 for two of your unknown EPM7128SLC84. We pay for our own shipping so no money is involved. I've had a few EPM7128S with JTAG locked but was not successful unlocking them with 12V (I was more successful unlocking EPM7064S), so I like to try again with yours.
Bill
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| Re: CPLD Trainer with 6502, Z80, and more... [message #10014 is a reply to message #10013] |
Fri, 15 July 2022 18:23 |
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berzerkula
Messages: 17
Registered: May 2020
Location: Arkansas, USA
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 plasmo wrote on Wed, 13 July 2022 19:01William,
Your board looks good. The connection to CPLD is very simple, just the programming header plus two 4.7K resistors associated with pull up & pull down of JTAG signals. There are very little that can go wrong, JTAG programming header is actually 2x5 header, but I have had a large supply of surplus headers with pin 10 missing which is a redundant ground pin. The missing pin 10 helps me identify which way the JTAG programming ribbon should be positioned (ribbon with strip side goes to pin 1). I see you have the same arrangement as well. I think your assessment of used CPLD with locked JTAG is the most likely answer.
Completely unused EPM7128SLC84 from factory should draw very little current (under 5mA). With USB blaster attached it may draw 50mA. 120mA to 260mA is not excessive for programmed CPLD, so it is still possible you have a real EPM7128SLC84.
Since you live in the States, I'll propose a swap: two of my proven EPM7128SLC84 for two of your unknown EPM7128SLC84. We pay for our own shipping so no money is involved. I've had a few EPM7128S with JTAG locked but was not successful unlocking them with 12V (I was more successful unlocking EPM7064S), so I like to try again with yours.
Bill
Hello Bill,
I received the Altera UP1 University Program board from UM-Columbia and my USB-Blaster was able to autodetect the EPM7128SLC84-7 that comes with it. I inserted the device into the CPLD trainer board and the USB-Blaster was able to autodetect and program it. Unprogrammed, it was only drawing about 40mA. I'll get with you next week about sending the questionable EPM7128SLC84-10's. I put one of the questionable devices in the UP1 board, and it couldn't auto-detect it when in there, however when I did turn it on, some of the segments of the UP1 board did light up, so something was already programmed in them.
My next issue is as follows:
After programming the working EPM7128SLC84-7, I was unable to see any segments lit. I turned off the lights in the room and covered the segments with my hand and I could very faintly see RED segments A-G lit. I'm using TDSL5160 Common Cathode as in this datasheet TDSL51 Now with r1 schematic, 150 ohm resistors are installed for segments A-G + DP, 4.7K for the emitter of the 2N2222A's. While powered on and running, I put a 1.8k in parallel with the 4.7k and it became brighter but not as bright as you have in pictures/videos. Anything I can check there? Voltage at 2N2222A collector is 1.9V, base at 0.577V. Voltage on common side of 4.7K to 7Segment is 3.278V. 2V forward Voltage of the segment leaves 1.278V. So at 150ohms, that is only 8mA whereas the forward current needs to be 20mA in the datasheet. Am I looking at this right? I setup the same conditions on a bread board, not exact voltages, but at 3.268V, I get 0.580V at base. 1.67V at collector to segment. 7 to 8mA to segment making it very dim. So, it seems for my setup I need to adjust the common base resistor. What are your thoughts with this?
-William
You feel a whole lot more like you do now than you did when you used to.
[Updated on: Mon, 18 July 2022 11:25] Report message to a moderator |
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| Re: CPLD Trainer with 6502, Z80, and more... [message #10016 is a reply to message #10015] |
Sat, 16 July 2022 00:33 |
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berzerkula
Messages: 17
Registered: May 2020
Location: Arkansas, USA
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Junior Member |
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 plasmo wrote on Fri, 15 July 2022 22:43William,
The base voltage of 0.577V is about right but collector voltage of 1.9V is not right. 4.7K base resistor is admittedly a tad high so your choice of 1.8K maybe a better value. However, 2N2222 has a nominal gain of 100 so even the 4.7K base resistor should still resulted in collector current of 50mA and collector voltage of 0.5V or lower. I suspect your 2N2222 may have different emitter-base-collector assignment. The base pin is probably correct but maybe the emitter and collector pins are swapped?
Your display is rated at 15mA per segment so 8mA per segment should be fairly bright. The CPLD output high current is limited so it won't be able to source 15mA per segment but should be able to source 8mA per segment.
Bill
Hello Bill,
What do you know, can't always trust the orientation of the device via the curve and flat end. Indeed, the collector and emitter pins 1 and 3 are swapped with the 2N2222A's on hand. Diotec 2N2222A If I had the 2N2222B's then it'd be right. Thank you for the tip. I would have missed it! Session 1 is a success.
I spent a lot of time making sure the supervisory IC's had the right pinouts, the 2N2222A's I had were neglected.
-William
You feel a whole lot more like you do now than you did when you used to.
[Updated on: Sat, 16 July 2022 01:13] Report message to a moderator |
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| Re: CPLD Trainer with 6502, Z80, and more... [message #10017 is a reply to message #9754] |
Sat, 16 July 2022 02:20 |
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berzerkula
Messages: 17
Registered: May 2020
Location: Arkansas, USA
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 Greetings,
Session 2 went well. I installed the rest of the 7 segment displays and the 2N2222A's. Almost bit myself again following the guide, but rectified it and all are driving properly now. Tested with both a DIP14 and DIP8 canned oscillator. The result is attached.
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Attachment: SESSION2.gif
(Size: 9.59MB, Downloaded 1246 times)
You feel a whole lot more like you do now than you did when you used to.
[Updated on: Sat, 16 July 2022 02:21] Report message to a moderator |
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| Re: CPLD Trainer with 6502, Z80, and more... [message #10018 is a reply to message #10017] |
Sat, 16 July 2022 07:40 |
plasmo
Messages: 889
Registered: March 2017
Location: New Mexico, USA
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Excellent! Once you have figured out the CPLD development process, the rest should go rapidly. Even the addition of microprocessor should work out because it can utilize the CPLD to debug the processor. My current work with 6809 is going well simply because I have the CPLD to provide diagnostic help. CPLD datasheet specifies 100 times reprogramming of CPLD, but that's conservative by probably one order of magnitude, I.e., you probably can reprogram it 1000 times.
You may find the 7-seg display not very helpful once you have the processor running at full speed,; so for next board you build, you may want to socket the 7-seg display. This way you can remove the display and plug in a daughterboard that reuse the 14 CPLD I/O originally used by the display.
Bill
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| Re: CPLD Trainer with 6502, Z80, and more... [message #10033 is a reply to message #10018] |
Wed, 27 July 2022 22:34 |
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berzerkula
Messages: 17
Registered: May 2020
Location: Arkansas, USA
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Hello Bill,
Going well here with the progress. Session 5 is a success. I was having issues getting the same results as you, until I fixed pin 84 in my socket. It got mangled, but now with correct contact, I get same results, now.
-William
You feel a whole lot more like you do now than you did when you used to.
[Updated on: Wed, 27 July 2022 22:43] Report message to a moderator |
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| Re: CPLD Trainer with 6502, Z80, and more... [message #10034 is a reply to message #10033] |
Thu, 28 July 2022 00:48 |
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berzerkula
Messages: 17
Registered: May 2020
Location: Arkansas, USA
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Went to serial output and all I get is something like the following for serial. Using the common FT232RL breakouts, had to use wires as the pinouts don't match up to what your device has. Which device is that which you use?
Seems at pin 61 from the CPLD to P2 TX ( to the FT232RL RX) may be something wrong. I'll probe it later on. At least Session 5 is a success. Session 6 and 7 looks like it will be fun getting serial working properly. 115200 8N1 no flow control is how I have the serial configuration.
You feel a whole lot more like you do now than you did when you used to.
[Updated on: Thu, 28 July 2022 00:48] Report message to a moderator |
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| Re: CPLD Trainer with 6502, Z80, and more... [message #10038 is a reply to message #10036] |
Sat, 30 July 2022 10:35 |
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berzerkula
Messages: 17
Registered: May 2020
Location: Arkansas, USA
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Hello Bill,
I now see activity at the serial port with the Simple TX session:
Will work up to Session 7 next. I have become familiar with Quartus II and VHDL. What I did was build up the logic from a project for the Altera UP2 board and had the 2 seven segment displays counting up to 00-FF.
It is from the University of Montenegro Faculty of Electrical Engineering, and is a great guide to get my feet wet in Quartus II and Modelsim-Altera.
I did modify the logic so it counts 0-F and not 0-9 for BCD.
Two Digit Seven Segment Counter
-William
You feel a whole lot more like you do now than you did when you used to.
[Updated on: Sat, 30 July 2022 10:37] Report message to a moderator |
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| Re: CPLD Trainer with 6502, Z80, and more... [message #10039 is a reply to message #10038] |
Sat, 30 July 2022 12:05 |
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berzerkula
Messages: 17
Registered: May 2020
Location: Arkansas, USA
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Greetings,
Session 7 is a success. I am using an SST39SF040 and inserted the CPLD program at location 0007FFF0-0007FFFF and am receiving the same text in the terminal. So far, so good! Thanks for looking at the changes for r1 PCB's, Bill.
For Session 8, I was able to get the Memory Diagnostic going. I have been getting a lot of OK's, so that is okay! Reminds me of when ya would power on the CTS256A-AL2 Code-To-Speech chip with the SPO256A-AL2, and when the system was ready it would output in its mechanical monotone voice, "O-Kay."
Now we just need to work up serial input next.
-William
You feel a whole lot more like you do now than you did when you used to.
[Updated on: Sat, 30 July 2022 16:11] Report message to a moderator |
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| Re: CPLD Trainer with 6502, Z80, and more... [message #10042 is a reply to message #10041] |
Sat, 30 July 2022 18:13 |
plasmo
Messages: 889
Registered: March 2017
Location: New Mexico, USA
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I have not documented session 11 which has a better serial transmitter with status bit. I also added additional functions to the CPLD until it is full (99% macrocell utilization, 100% I/O utilization). The additional functions are "flash programmer" that was described here:
http://forum.6502.org/viewtopic.php?f=10&t=6974&star t=15#p90790
I also added a 100hz interrupt and I2C interface. These two functions have not been tested.
Attached is monitor program for session 11 (TrainMon v0.3). Since the trainer with session 11 CPLD can program itself, you can try to load the monitor into flash without using a separate flash programmer.
Assuming you have 55nS RAM like AS6C4008, you should be able to run your hardware at 14.7MHz. My current project is making the trainer into a VGA controller that overclock the W65C02 to 25.175MHz to drive a VGA display directly. For it to run 25.175MHz, you'll need to add a wait state for flash access and use 25nS or faster RAM, but it is entirely do-able.
Picture of CPLD trainer with 25nS RAM running at 25.175MHz
Bill
[Updated on: Sat, 30 July 2022 18:14] Report message to a moderator |
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| Re: CPLD Trainer with 6502, Z80, and more... [message #10043 is a reply to message #10042] |
Sat, 30 July 2022 18:21 |
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berzerkula
Messages: 17
Registered: May 2020
Location: Arkansas, USA
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plasmo wrote on Sat, 30 July 2022 20:13
Assuming you have 55nS RAM like AS6C4008, you should be able to run your hardware at 14.7MHz. My current project is making the trainer into a VGA controller that overclock the W65C02 to 25.175MHz to drive a VGA display directly. For it to run 25.175MHz, you'll need to add a wait state for flash access and use 25nS or faster RAM, but it is entirely do-able.
Picture of CPLD trainer with 25nS RAM running at 25.175MHz
Bill
Hello Bill,
Thanks for the update. I was looking to using the WDC 65C02 to drive VGA in the past and saw it could easily do 24MHz or more by itself. Interesting you mention this! Yes, I do use the AS6C4008-55PCN. So I should have no issues. This is great news! Really looking forward to completing these next sessions.
-William
You feel a whole lot more like you do now than you did when you used to.
[Updated on: Sat, 30 July 2022 19:21] Report message to a moderator |
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| Re: CPLD Trainer with 6502, Z80, and more... [message #10044 is a reply to message #10042] |
Sat, 30 July 2022 19:17 |
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berzerkula
Messages: 17
Registered: May 2020
Location: Arkansas, USA
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Junior Member |
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Hello Bill,
Success! Session 11 is a go.
Had no issue with the previous monitor, either. I am up to the 14.7456MHz crystal oscillator at 230400 baud.
Now to have some fun! This is exciting. I will attempt to write the flash in-situ.
-William
You feel a whole lot more like you do now than you did when you used to.
[Updated on: Sat, 30 July 2022 19:22] Report message to a moderator |
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| Re: CPLD Trainer with 6502, Z80, and more... [message #10317 is a reply to message #9754] |
Tue, 18 April 2023 23:44 |
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berzerkula
Messages: 17
Registered: May 2020
Location: Arkansas, USA
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Junior Member |
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Hello,
It has been almost a year since getting back to this. Do you have project files to include? I was thinking to go with the rest of the training sessions we had. The main thing I want to work with is VGA, the last session I was successful is 11.
Is VGA session 12? If so, I'd like to get the details like the previous sessions. Your project and sessions are excellent to help me along. I have some Altera UP1, UP2, DE2 and other dev boards and a lot of EPM7128SLC84-{10,7,6} devices I'd like to use. So this is helping me a lot.
Sincerely,
William
You feel a whole lot more like you do now than you did when you used to.
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| Re: CPLD Trainer with 6502, Z80, and more... [message #10318 is a reply to message #10317] |
Wed, 19 April 2023 17:33 |
plasmo
Messages: 889
Registered: March 2017
Location: New Mexico, USA
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Senior Member |
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Hi William,
The trainer project is getting complicated because now it can accommodate a number of different processors. Initially I started with W65C02 and have published 10 sessions as part of development with W6502 (session 11 is still not published, I'll get to it eventually). I also have Z80-based designs as well as 6809-based designs, but they are not so well documented. CPLD trainer has also evolved into a general-purpose experimental board so I have front-panel, Ben Eater emulator, VGA-beam racing, and other experiments that are not published. I'm happy to share whatever information I have, but like most engineers, I'm always behind in documentation!
I think Session 11 is the end of the CPLD training. After that are various projects using a particular microprocessor. So I'll post VGA controller as one of the W65C02 projects. I should have the design information uploaded in a couple days and will update this post with the link.
EPM7128 is a very capable device. You can construct a standalone computer completed with keyboard, VGA, hard disk using EPM7128. My current activity is [url=https://www.retrobrewcomputers.org/forum/index.php?t=ms g&th=512&goto=10254&#msg_10254]Z80all[/url] which is a Z80 SBC with 4 chips plus CF disk. I'm delighted to have Ladislau Szilagyi developing complete tool chains of editor/assembler/c compiler specifically for Z80all. I believe a similar design based on W65C02 overclocked to 25MHz is also possible.
Bill
4/22/23 update. Created a page for VGA beam racing with 6502 CPLD trainer.
[Updated on: Sat, 22 April 2023 21:20] Report message to a moderator |
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