Home » RBC Forums » General Discussion » End year rant: starting a new design, the STUDIO 68 board for "experiments"... (A retro FPGA-centric board (68SEC000, STM32F030R8T6, EP2C8Q208, 16MW SDRAM))
| End year rant: starting a new design, the STUDIO 68 board for "experiments"... [message #9476] |
Mon, 13 December 2021 02:40  |
 |
just4fun
Messages: 273
Registered: May 2017
Location: Dark side of the Moon
|
Senior Member |
|
|
It is something I'm thinking about during the last months and now I've some time to start developing it...
STUDIO 68 is a new ongoing design for a board to make "experiments". It has a 68SEC000 CPU, a STM32F030R8T6 MCU + USB + SD, a 16MWord SDR DRAM and a 208pin FPGA. It will be possible use the same approach to virtual HW using the STM32 MCU as done for the 68k-MBC, or synthesize it inside the FPGA (or a mix of both).
Two main connectors: the GPIO and the EB (External Bus). The (SHARED) GPIO allows to use little add-on boards/adapters as the one to give a VGA/KB output (the VGA/KB core must be implemented inside the FPGA). The EB is a real complete external bus RC2014 compatible. It will allows to add a board for virtually any CPU to make experiments and emulate peripherals HW inside the FPGA (a first application will probably be an "application board" for a soviet PDP11 CPU clone):
Here the EB (External Bus) pinout (compared with the BP80/RC2014 enhanced bus it has 4 pins less to fit into a 100 x 100 mm 4-layer board, anyway the pinout should allow optimal compatibility). The various "control buses" (LCBn, ECB) are directly managed inside the FPGA, including the control signals (ECB) of the external bus. This should give a virtually complete HW reconfiguration capability, so it should be possible create virtual HW/peripherals for any legacy CPU. The external bus drivers have the Partial-Power-Down Mode and Back Drive protection, so the "target CPU board" connected to the external bus can have an independent power supply to accommodate power hungry CPUs:
So we'll see...
-
Attachment: Ext_Bus.jpg
(Size: 184.77KB, Downloaded 1991 times)
-
Attachment: Studio 68.jpg
(Size: 149.33KB, Downloaded 2061 times)
[Updated on: Thu, 03 February 2022 07:12] Report message to a moderator |
|
|
|
|
|
|
|
|
|
|
|
| Re: End year rant: starting a new design, the STUDIO 68 board for "experiments"... [message #9488 is a reply to message #9480] |
Tue, 14 December 2021 02:35  |
|
just4fun
Messages: 273
Registered: May 2017
Location: Dark side of the Moon
|
Senior Member |
|
|
@gbm:
Yes, but currently all the GPIO are used, so some more analysis is required. I'll think about it, but to be honest is not on top of my priorities...
BTW: from the Mouser catalog the F072 costs about twice the F030 (that is one of the cheapest 64pin STM32 with at least 64KB flash), so I think that there are cheaper parts with an USB as may be the STM32F070RBT6 that has 128KB flash.
@plasmo:
The STUDIO 68 can be used with different target CPU too (holding the 68SEC000 Address and Data bus in High Z) using an "application board" on the External Bus (EB). In this case, if the target CPU is something like an 8086 you need a 16 lines data bus and a 20 lines address bus (all the RAM and the various peripherals are hosted inside the STUDIO 68 board that acts as slave).
[Updated on: Tue, 14 December 2021 03:22] Report message to a moderator |
|
|
|
|
|
|
|
| Re: End year rant: starting a new design, the STUDIO 68 board for "experiments"... [message #9769 is a reply to message #9764] |
Mon, 21 February 2022 15:16 |
coredump
Messages: 33
Registered: January 2020
Location: Germany
|
Member |
|
|
just4fun wrote on Tue, 15 February 2022 13:58
I've attached the current untested draft of the schematic.
Hi Fabio,
very well done, as usual.
And very interesting. Please keep us up to date :)
But I have a remark may be worth a few lines.
It's about Q5 that, what I understood, should supply eg. an other processor with a clock signal.
Simple saturated switches, especially those switching low currents with rather slow transistors intended
to switch higher currents, can be disappointingly slow.
With,say, a 5MHz...10MHz clock I assume the output might stick all time at a LOW-level enjoying the storage time of the
2n2222-derivative and the small cut-off current involved.
The slow transistor problem can be circumvented with something like mmbt2369A.
The cut-off base current can be improved with a small C || R27.
But the rise time of the output is than determined by R29 and the load capacitance.
With a load around 50pF (transistor, traces, clock-input, 1:10 oscilloscope probe) and an desirable
RC time of 5...10ns R27 would be in the 100...200 Ohm range.
Maybe simpler, faster and less current sucking would be a 74AHCT1G04 supplied from the external 5V.
It is tolerant to input signals without applied supply, translates the 3V3 world to 5V CMOS, is faster and quite hassle free compared to a saturated switch and requires only a bypass C, a pullup/down R on the input (tri-stated port) and maybe a series termination on the output. If I didn't missinterpret the intention behind Q5 it might make things maybe a little bit simpler.
Best Regards
Detlef
[Updated on: Mon, 21 February 2022 15:56] Report message to a moderator |
|
|
|
| Re: End year rant: starting a new design, the STUDIO 68 board for "experiments"... [message #9777 is a reply to message #9769] |
Thu, 24 February 2022 02:01 |
|
just4fun
Messages: 273
Registered: May 2017
Location: Dark side of the Moon
|
Senior Member |
|
|
Hi coredump,
the EBE-CLK line is not intended to give the clock to an external board (yes... the name is misleading...) but to give a single setup pulse to the "Studio 68 EB Expander board" (EBE board) to setup its internal logic just after the power on.
Some more explanation is needed here. The EB bus is made to be HW independent, so all the 16 EB control lines (EB19-EB26, EB57-EB64) are managed by the FPGA. But also the direction of each of these 16 lines need to be configurable, so for a given CPU it must be possible to choose the Clock and the other control lines like i.e. RD, WR or WAIT and assign them to any of the 16 control lines of the EB bus. But using a "conventional" driver this means to add a DIR control line for each EB control line, and this adds the need of 16 more pins of the FPGA (yes... a tradeoff could be use 4 groups of 4 drivers, so only 4 more DIR lines are needed, but this "eats" FPGA pins anyway and lowers the flexibility...). To avoid this I've used "smart drivers" (TXB0108PW) that can auto-sense the direction of each control line, so more DIR lines are not needed. Unfortunately these "smart driver" are very sensitive to the length of the line and its capacitance and may auto oscillate if the specifications are not respected. So I've restricted to only two bus connectors on the main board. More, must be careful designing the boards to be plugged on the EB bus to avoid auto oscillations of the TXB0108PW drivers. So for a real RC2014 compatibility I've designed an EB Expander board (EBE board) that adds 16 conventional bidirectional buffers between the EB bus control lines and the hosted (true) RC2014 connectors. But these drivers need to be set to the proper direction before normal operations, and this is done using the 16 data lines together with the EBE-CLK line to set each control line direction as needed. To have a better idea of that, I've added the EBE board schematic draft (see attachment).
Anyway thank you for the suggestions. You are right about Q5, and a single gate IC would be perfect for a clock line. In this case I'll probably use a 2N7002 MOSFET with a 1k pullup. I've used and tested this configuration for asynchronous transmissions up to 1Mbs and I think that it is here a good tradeoff (the EBE-CLK line it is normally at "1", so no power is wasted inside the pullup after the initial single setup pulse at the power on). May be also a better name for EBE-CLK can be a good idea... something like EBE-SETUP.
Fabio.
[Updated on: Thu, 24 February 2022 02:11] Report message to a moderator |
|
|
|
|
|
|
|
| Re: End year rant: starting a new design, the STUDIO 68 board for "experiments"... [message #10000 is a reply to message #9870] |
Sun, 03 July 2022 02:30 |
|
just4fun
Messages: 273
Registered: May 2017
Location: Dark side of the Moon
|
Senior Member |
|
|
I'm currently preparing the last things for a first test run of the 68SEC000 CPU:
I've decided for now to use the internal RAM blocks of the FPGA (M4K blocks) instead of the SDRAM to keep things easier because I need at first to test (on the real HW) the VHDL design of all the I/O logic.
This way I've 13KB RAM, enough to test I/O (serial port + control logic).
The 68SEC000 CPU for now is set to work with an 8 bit data bus (like a 68008).
The STM32 will take care to read all the outgoing data from the I/O output register and send it to the USB, and to do the same with the incoming data from USB, so some FW will be needed, but this one should be simple.
More, using FPGA M4K RAM blocks allows to easily preload the content of the RAM directly from the JTAG stream using a .mif binary image file, so in this phase I don't need to make a bootloader FW for the 68SEC000 CPU on the STM32 side:
The VHDL design is eating a lot of time, but this was expected (and playing with VHDL was one of the main motivations to build this board...).
We'll see...
[Updated on: Mon, 04 July 2022 00:13] Report message to a moderator |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Current Time: Sat Mar 15 19:39:31 PDT 2025
Total time taken to generate the page: 0.00768 seconds
|
RetroBrew Computers Forum
Members
Search
Help
Login
Home
