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DMA with 68020/68030/68040 CPU's [message #8839] Mon, 12 July 2021 22:09 Go to next message
kkeeley is currently offline  kkeeley
Messages: 26
Registered: July 2017
Location: Melbourne - Australia
Junior Member
Hi all,

I'm doing some research into adding DMA to my 68030 based system that I've been designing for years. My question are:

1) What DMA controllers where used with the 680x0 based chips where 32-bit data transfers where required?

2) I've seen a few examples of 68450's being used with these CPU's but from what I read this is only a 8/16 bit data bus and 24 bit address bus, so how where these configured to be able to acess the entire 32-bit address space and preform 32 bit transfers?

Thanks in advance for any information.

Kenneth
Re: DMA with 68020/68030/68040 CPU's [message #8845 is a reply to message #8839] Tue, 13 July 2021 16:23 Go to previous messageGo to next message
coredump is currently offline  coredump
Messages: 33
Registered: January 2020
Location: Germany
Member
Hi Kenneth,
kkeeley wrote on Tue, 13 July 2021 07:09
Hi all,

I'm doing some research into adding DMA to my 68030 based system that I've been designing for years. My question are:

1) What DMA controllers where used with the 680x0 based chips where 32-bit data transfers where required?

The MC68(EN)360 used as a companion to the 68030 offers 2 external DMA channels (and much more...).
A few peripherals like national's DP83932 come with an internal DMA-controller.

But since the majority of peripherals used to be 8 Bit and 16 Bit, the MC68442 (or late versions of the 68440 in 68pin packages) offered a low latency solution with full 32Bit address range but only 16Bit at a time data transfer with rather low performance (4 clock cycles per transfer, low clock speed (10MHz??)).

Quote:


2) I've seen a few examples of 68450's being used with these CPU's but from what I read this is only a 8/16 bit data bus and 24 bit address bus, so how where these configured to be able to acess the entire 32-bit address space and preform 32 bit transfers?

Maybe a 68440/68442 instead of the 68450?
The MC68851 PMMU manual has an example on page 292 (third edition, PDF page number) with the 68442 on the logical Bus side of the PMMU (Figure B-2) for 16 Bit transfers.
Figure B-3 and the text should make quite clear how the 16 Bit bus of the DMA controller is connected to the 32-bit bus.

Best Regards
Detlef


Re: DMA with 68020/68030/68040 CPU's [message #8846 is a reply to message #8845] Tue, 13 July 2021 16:51 Go to previous messageGo to next message
kkeeley is currently offline  kkeeley
Messages: 26
Registered: July 2017
Location: Melbourne - Australia
Junior Member
Hi Derlef,

Thanks for the information, that's very interesting information as I had not noticed that the MC68442 had a 32-bit address bus.

I haven't been able to locate a full version of the MC68851 manual that you mention, all I've managed to find so far is what appears to be an abstract of the document containing about 47 pages, unfortunately the pages you mention aren't part of it. Do you have a link to where you found your copy?

Thanks again
Kenneth
Re: DMA with 68020/68030/68040 CPU's [message #8847 is a reply to message #8846] Tue, 13 July 2021 17:17 Go to previous messageGo to next message
coredump is currently offline  coredump
Messages: 33
Registered: January 2020
Location: Germany
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http://bitsavers.trailing-edge.com/components/motorola/68000 /MC68851_PMMU_Users_Manual_1ed_1986.pdf

An older edition, pdf-page 282.

Best Regards
Detlef
Re: DMA with 68020/68030/68040 CPU's [message #8848 is a reply to message #8847] Tue, 13 July 2021 17:34 Go to previous messageGo to next message
kkeeley is currently offline  kkeeley
Messages: 26
Registered: July 2017
Location: Melbourne - Australia
Junior Member
Thank you, I'll have a read of this and see if I can make sense of it all.

Kenneth
Re: DMA with 68020/68030/68040 CPU's [message #8853 is a reply to message #8846] Wed, 14 July 2021 15:31 Go to previous messageGo to next message
coredump is currently offline  coredump
Messages: 33
Registered: January 2020
Location: Germany
Member
kkeeley wrote on Wed, 14 July 2021 01:51
Hi Derlef,

Thanks for the information, that's very interesting information as I had not noticed that the MC68442 had a 32-bit address bus.

Since he 68442 is often hard to find and rather expensive: The MC68440 in PLCC and PGA package with date code 8936 or newer also have the 32 Bit address bus. Especially the PLCC variant is often quite cheap.
But it misses the special look of the golden hat, of course.

Best Regards
Detlef

Re: DMA with 68020/68030/68040 CPU's [message #10236 is a reply to message #8853] Thu, 09 February 2023 10:37 Go to previous messageGo to next message
tomstorey is currently offline  tomstorey
Messages: 7
Registered: January 2022
Junior Member
Hi,

Wanted to drag this thread up to find out what solution you came to in the end. The 68442 is gold dust as far as I can tell, and the 68440 is less plentiful than the 68450, but the ones that I do see available all appear to be after the 8936 date code, so thats a good sign.

But I had a thought, inspired by the IBM PC/XT/AT. These systems use an addressable register into which you can write a "page", and during DMA transfers that page number is output onto the adress bus as higher address bits. The DMA controllers used in these systems are only capable of addressing 64KB on their own but the machines contain much more than this, so this paging mechanism, while not perfect, allows you to DMA to/from extended address ranges.

A small 8 bit RAM could serve the same purpose, providing up to 256 pages of 16MB each. A bit of muxing and some arbitration circuitry would be required to allow the RAM to be read/written by the CPU to configure the pages, or the DMA controller to use it as a source of additional address bits. I imagine:

* The data bus can be either switched to the system data bus to allow CPU read/write, or unidirectionally onto A31..24
* A couple of the lower bits of the address bus can be either switched to the system address bus for CPU read/write, or to some combination of DMA channel and the read/write signal to select the appropriate page number for reading/writing

And it does mean a bit of extra software work to calculate the maximum size of a block that can be transferred to keep it within a source or destination 16MB window, but .. 4 DMA channels with 32 bit addressing and up to 16MB transfers at a time, not too bad for a few extra chips. Smile
Re: DMA with 68020/68030/68040 CPU's [message #10237 is a reply to message #10236] Thu, 09 February 2023 15:00 Go to previous message
kkeeley is currently offline  kkeeley
Messages: 26
Registered: July 2017
Location: Melbourne - Australia
Junior Member
Hi Tomstorey,

To be honest, I haven't spent much time looking into adding a DMA controller to my design since raising this question.
Your idea seams intersting and worth considering if I do decide to go ahead with a DMA controller design.

Kenneth.
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