DMA with 68020/68030/68040 CPU's [message #8839] |
Mon, 12 July 2021 22:09  |
kkeeley
Messages: 26 Registered: July 2017 Location: Melbourne - Australia
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Junior Member |
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Hi all,
I'm doing some research into adding DMA to my 68030 based system that I've been designing for years. My question are:
1) What DMA controllers where used with the 680x0 based chips where 32-bit data transfers where required?
2) I've seen a few examples of 68450's being used with these CPU's but from what I read this is only a 8/16 bit data bus and 24 bit address bus, so how where these configured to be able to acess the entire 32-bit address space and preform 32 bit transfers?
Thanks in advance for any information.
Kenneth
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Re: DMA with 68020/68030/68040 CPU's [message #10236 is a reply to message #8853] |
Thu, 09 February 2023 10:37   |
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tomstorey
Messages: 7 Registered: January 2022
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Junior Member |
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Hi,
Wanted to drag this thread up to find out what solution you came to in the end. The 68442 is gold dust as far as I can tell, and the 68440 is less plentiful than the 68450, but the ones that I do see available all appear to be after the 8936 date code, so thats a good sign.
But I had a thought, inspired by the IBM PC/XT/AT. These systems use an addressable register into which you can write a "page", and during DMA transfers that page number is output onto the adress bus as higher address bits. The DMA controllers used in these systems are only capable of addressing 64KB on their own but the machines contain much more than this, so this paging mechanism, while not perfect, allows you to DMA to/from extended address ranges.
A small 8 bit RAM could serve the same purpose, providing up to 256 pages of 16MB each. A bit of muxing and some arbitration circuitry would be required to allow the RAM to be read/written by the CPU to configure the pages, or the DMA controller to use it as a source of additional address bits. I imagine:
* The data bus can be either switched to the system data bus to allow CPU read/write, or unidirectionally onto A31..24
* A couple of the lower bits of the address bus can be either switched to the system address bus for CPU read/write, or to some combination of DMA channel and the read/write signal to select the appropriate page number for reading/writing
And it does mean a bit of extra software work to calculate the maximum size of a block that can be transferred to keep it within a source or destination 16MB window, but .. 4 DMA channels with 32 bit addressing and up to 16MB transfers at a time, not too bad for a few extra chips.
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Re: DMA with 68020/68030/68040 CPU's [message #10237 is a reply to message #10236] |
Thu, 09 February 2023 15:00  |
kkeeley
Messages: 26 Registered: July 2017 Location: Melbourne - Australia
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Junior Member |
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Hi Tomstorey,
To be honest, I haven't spent much time looking into adding a DMA controller to my design since raising this question.
Your idea seams intersting and worth considering if I do decide to go ahead with a DMA controller design.
Kenneth.
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