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Z80 interupt timing question [message #8345]

Tue, 23 February 2021 09:47

comwarrior
Messages: 11
Registered: April 2019

Junior Member

Greeting everyone.
I'm currently building up for MMRC test 3... Its a comms hardware test.

The upcomming Test 4 requires causing an interupt on the Z80.
Looking at the Z80 timing diagram the INT line is ascerted and then released at the last T state but my system isn't going to know when the last T State is occuring. Looking at the Z80 SIO interupt timing it suggests that you can ascert INT and keep it low untill IORQ and M1 are released.

So, can I get a sanity check. (from the hardware device) If i ascert INT, wait for M1 and IORQ to go low, put the vector on the data bus, wait for IORQ and M1 to go high and then release INT and data bus... Will this work without causing double ints or any other 'artifacts'?

TIA

CW

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Re: Z80 interupt timing question [message #8346 is a reply to message #8345]

Tue, 23 February 2021 10:43

wsm
Messages: 232
Registered: February 2017
Location: AB, Canada

Senior Member

I think you need to remember that once an INT is acknowledged, all interrupts except NMI are disabled until software re-enables them via the EI instruction. The INT* signal can be level oriented and remain active until reset by software. Double INTs are related to software not resetting the original INT* source before re-enabling them.

From a hardware peripheral standpoint in mode 2: Dvector = INTrequired + IEI + M1* + IORQ*

From a software standpoint:
...
INT processing
Reset source of INT
EI
RETI

Note that the effect of EI is deferred one instruction and doesn't occur until after the RETI. This prevents back-to-back INTs from creating multiple return addresses on the stack leading to overflow. Extra precautions are required if issuing the EI before the end of a long running interrupt routine.

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Re: Z80 interupt timing question [message #8347 is a reply to message #8346]

Tue, 23 February 2021 11:43

comwarrior
Messages: 11
Registered: April 2019

Junior Member

I completely forgot the Z80 disabled interupts, On PIC's you have to deliberatly disable them, which means you can have interupt jumps when your inside the interupt handler. Normally it will still figure them out and work its way out... or it'll cause a stack overflow and dissapear into the wild blue yonder. Unless you also have a stack overflow reset trap.
Long story short, tests 3 and 4 build an advanced SIO thats more like the IO portion of winbond / northbridge setup.
Test 4 is going to need me to program the Z80 with a terminal handler, shame i can't just grab and compile BASH...

Thank you for the info.

CW

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