| RC2014 Z80 /WR and /RD mutually exclusive? [message #8287] |
Thu, 04 February 2021 12:20  |
quarterturn
Messages: 86
Registered: April 2018
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On RC2014 Z80, are /WR and /RD always the opposite of each other, or can they both go low?
The reason for asking is I'm prototyping a MOS8568 video card for RC2014 and the MOS8568 has a single r + /w pin. The prototype board I'm using provides a 74LS32 to OR /WR, /RD, and /IORG into /IOWR and /IORD signals. If /WR and /RD are mutually exclusive, I could just connect /IOWR to r + /w. If not, it'll take more logic and I'm tight on extra board space.
Thanks!
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| Re: RC2014 Z80 /WR and /RD mutually exclusive? [message #8291 is a reply to message #8287] |
Fri, 05 February 2021 19:15  |
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If both /WR and /RD were low, the processor would be both writing to an address and reading from it at the same time. That doesn't make any sense. That would mean both the Z80 and the device at that address would put a byte on the data bus, which would result in some sort of collision. There would be no telling what either would get. So, it is safe to say they cannot be low at the same time, else it'd be an invalid system state.
Plus, I don't think the Z80 has any instructions which would cause such a state.
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| Re: RC2014 Z80 /WR and /RD mutually exclusive? [message #8301 is a reply to message #8287] |
Sun, 07 February 2021 01:26 |
beb
Messages: 10
Registered: October 2019
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Junior Member |
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quarterturn wrote on Thu, 04 February 2021 12:20On RC2014 Z80, are /WR and /RD always the opposite of each other, or can they both go low?
The reason for asking is I'm prototyping a MOS8568 video card for RC2014 and the MOS8568 has a single r + /w pin. The prototype board I'm using provides a 74LS32 to OR /WR, /RD, and /IORG into /IOWR and /IORD signals. If /WR and /RD are mutually exclusive, I could just connect /IOWR to r + /w. If not, it'll take more logic and I'm tight on extra board space.
Thanks!
First part of the answer : they *SHALL* never go low at the same time, as they used to control direction of bus transceivers. This would lead to bus contention and hardware damages. Moreover, for some transceivers like 74LS240, it is clearly required that both direction shall never be active at the same time, as it will make the chip oscillate (and probably destroy it)
Second part of the answer : if Zilog did put the two signals on two separate pins, it's because they have a good reason  (more pins means more copper to route, meaning higher costs)
If you look to 68xx or 6502, you will see that there is only one direction pin called R/nW, but this pin is associated to E pin, which says when the signal is active.
So you have only two possibilities to implement those signals :
- either one pin to say when you read and one pin to say when you write (Z80, 80x86, etc)
- or one pin to say what you do (reading or writing) and one pin to say when you do it
So in all cases, you will need two pins. So, for the MOS8568, you will need to emulate the E signal from the Z80 bus, otherwise the chip will never recognize the bus sequence.
And, as said in another post, as far as I know there is no official instruction to do it (maybe an hidden one can do, but I would not try to find it as it may seriously damage the computer)
Benoit
[Updated on: Sun, 07 February 2021 01:28] Report message to a moderator |
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