Hi Steve,

Another option to consider is the Atmel ATF1508AS series. These are in-production parts that are electrically compatible with the EPM7128S. They are programmed using WinCUPL (Windows only) via a $60 programmer from Atmel (ATDH1150USB).

Amtel has a tool, POF2JED, that they say will convert an Altera POF file into an ATF1508 compatible JED file for programming. I have not tried this myself, but it should allow one to use Quartus II (Linux or Windows) to write code for the ATF1508 using Verilog or VHDL (instead of WinCUPL). I plan to try this at some point.

If you use the Altera parts directly, you can get very cheap ($2-$3) programmers on Ebay, but you may have to buy 10 of them because the cheap ones aren't very reliable. Also, to source the EPM7128S, the general recommendation is to get them from UTSource.net.

(While I've used Xilinx's Spartan series FPGAs, I have not used their CPLDs.

-- Rob

Although it has a 3.3V core, you could also use the XC9572XL which is 5V tolerant and requires considerably less power than the 5V version. I've used the Xilinx XPLA3 series [XCR3xxxXL] in several designs ... again they're a 3.3V core but use MUCH LESS power. There's also Lattice's ispMACH 4000V series [LC4xxxV] which are 5V tolerant and can be had in faster speeds (as low as 2.5ns). Using CPLDs that are 5V tolerant but have a Vio of 3.3V allows them to be easily used without level translators in a mixed voltage design which I've done several times without problems.

The extra overhead for the 3.3V version is usually just a 3.3V regulator plus one or two capacitors. Of course there's a bit of extra PCB layout work and possibly a few extra Vio caps.

In the end, there's a lot of tradeoffs with price, speed, power, packages, availability, series breadth, tools etc. and you have to weigh which ones are important to you and your designs.

Thanks very much. Can the 3.3v CPLDs drive chip selects or RW signals on usually 5v memory or peripheral ICs? I'm particularly thinking if I have a 5v logic address and data busses but 3.3v signalling out of the CPLD. I don't think I would need additional 74xx logic on the output side to consider.

My MinZ-C design is primarily 5V with a Z180, 5V SRAM etc. and I used an XCR3064XL for pretty well all the glue logic plus a 25MHz SPI controller. On my MinZ-IO2 board I used an XCR3128XL for the glue logic plus address registers and level translation between the 5V Z180 and a 3.3V 8MB flash device. My NYOZ series base module also uses an XCR3128XL with a large mixture of 3.3V and 5V devices.

I second wsm's design approach. Once you have the JTAG programming header working, development board is really not necessary. You should always populate and program the CPLD first before populating the rest of active ICs.
Bill