Z80 IFF1 default at RESET [message #6086] |
Mon, 11 March 2019 18:46 |
alank2
Messages: 31 Registered: March 2019
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After releasing /RESET the interrupt mode=0, but what about the IFF1 and IFF2 flags? Are they reset to disabled/0?
If so, how can control panels feed something like a JMP instruction? I know I could put that at bytes 0, 1, and 2 in memory, but I was hoping to change the PC after releasing reset.
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Re: Z80 IFF1 default at RESET [message #6092 is a reply to message #6091] |
Tue, 12 March 2019 04:58 |
alank2
Messages: 31 Registered: March 2019
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Indeed; excellent link I enjoyed seeing how it would be done in hardware. I did something similar in software last night. (/SRDBL disables SRAM from responding even if /MREQ is asserted)
//assert srdbl (we want to feed a jmp instruction)
PORTJ&=~_BV(PORTJ_SRDBL_PIN_AL);
//data bus output
DDRA=0xff;
//jmp opcode
PORTA=0xc3;
//assert busrq
PORTG&=~_BV(PORTG_BUSRQ_PIN_AL);
//release z80
PORTG|=_BV(PORTG_RESET_PIN_AL);
//wait for asserted busack
while (PING & _BV(PORTG_BUSACK_PIN_AL))
;
//low byte address
PORTA=0x11;
//release busrq
PORTG|=_BV(PORTG_BUSRQ_PIN_AL);
//assert busrq
PORTG&=~_BV(PORTG_BUSRQ_PIN_AL);
//wait for asserted busack
while (PING & _BV(PORTG_BUSACK_PIN_AL))
;
//high byte address
PORTA=0x22;
//release busrq
PORTG|=_BV(PORTG_BUSRQ_PIN_AL);
//assert busrq
PORTG&=~_BV(PORTG_BUSRQ_PIN_AL);
//wait for asserted busack
while (PING & _BV(PORTG_BUSACK_PIN_AL))
;
//data bus input
DDRA=0;
PORTA=0;
//deassert srdbl
PORTJ|=_BV(PORTJ_SRDBL_PIN_AL);
//release busrq
PORTG|=_BV(PORTG_BUSRQ_PIN_AL);
[Updated on: Tue, 12 March 2019 04:58] Report message to a moderator
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