RetroBrew Computers Forum
Discussion forum for the RetroBrew Computers community.

Home » RBC Forums » General Discussion » Z80 IFF1 default at RESET
Z80 IFF1 default at RESET [message #6086] Mon, 11 March 2019 18:46 Go to next message
alank2 is currently offline  alank2
Messages: 31
Registered: March 2019
Member
After releasing /RESET the interrupt mode=0, but what about the IFF1 and IFF2 flags? Are they reset to disabled/0?

If so, how can control panels feed something like a JMP instruction? I know I could put that at bytes 0, 1, and 2 in memory, but I was hoping to change the PC after releasing reset.
Re: Z80 IFF1 default at RESET [message #6087 is a reply to message #6086] Mon, 11 March 2019 19:33 Go to previous messageGo to next message
wsm is currently offline  wsm
Messages: 226
Registered: February 2017
Location: AB, Canada
Senior Member
The Z80 User Manual clearly states that upon RESET IEF1 and IEF2 are both zero (i.e. interrupts masked just like DI) and the Mode is set to 0.

As I remember, some of the panels used the trick of inhibiting the data bus and just supplying NOPs (i.e. opcode 00) until the restart address was reached at which time normal memory fetches occurred. The other option was to also inhibit the data bus but respond to the first memory read after RESET with a JMP (opcode 0C3h) followed by responses of the actual execution address (N.B. little endian).
Re: Z80 IFF1 default at RESET [message #6088 is a reply to message #6087] Mon, 11 March 2019 19:39 Go to previous messageGo to next message
alank2 is currently offline  alank2
Messages: 31
Registered: March 2019
Member
Thanks wsm, that second method sounds like it will work well.
Re: Z80 IFF1 default at RESET [message #6091 is a reply to message #6088] Tue, 12 March 2019 04:42 Go to previous messageGo to next message
etchedpixels is currently offline  etchedpixels
Messages: 333
Registered: October 2015
Senior Member
The magic words for the above in the S100 world were "power on jump": there's a modern example at http://www.glitchwrks.com/2013/04/17/power-on-jump.
Re: Z80 IFF1 default at RESET [message #6092 is a reply to message #6091] Tue, 12 March 2019 04:58 Go to previous message
alank2 is currently offline  alank2
Messages: 31
Registered: March 2019
Member
Indeed; excellent link I enjoyed seeing how it would be done in hardware. I did something similar in software last night. (/SRDBL disables SRAM from responding even if /MREQ is asserted)

    //assert srdbl (we want to feed a jmp instruction)
    PORTJ&=~_BV(PORTJ_SRDBL_PIN_AL);

    //data bus output
    DDRA=0xff;

    //jmp opcode
    PORTA=0xc3;

    //assert busrq
    PORTG&=~_BV(PORTG_BUSRQ_PIN_AL);

    //release z80
    PORTG|=_BV(PORTG_RESET_PIN_AL);

    //wait for asserted busack
    while (PING & _BV(PORTG_BUSACK_PIN_AL))
      ;

    //low byte address
    PORTA=0x11;

    //release busrq
    PORTG|=_BV(PORTG_BUSRQ_PIN_AL);

    //assert busrq
    PORTG&=~_BV(PORTG_BUSRQ_PIN_AL);

    //wait for asserted busack
    while (PING & _BV(PORTG_BUSACK_PIN_AL))
      ;

    //high byte address
    PORTA=0x22;

    //release busrq
    PORTG|=_BV(PORTG_BUSRQ_PIN_AL);

    //assert busrq
    PORTG&=~_BV(PORTG_BUSRQ_PIN_AL);

    //wait for asserted busack
    while (PING & _BV(PORTG_BUSACK_PIN_AL))
      ;

    //data bus input
    DDRA=0;
    PORTA=0;

    //deassert srdbl
    PORTJ|=_BV(PORTJ_SRDBL_PIN_AL);

    //release busrq
    PORTG|=_BV(PORTG_BUSRQ_PIN_AL);

[Updated on: Tue, 12 March 2019 04:58]

Report message to a moderator

Previous Topic: Building a 22MHz Z80 Computer in 4 Stages
Next Topic: Any Interest in OS9 68K


Current Time: Tue Apr 30 05:23:52 PDT 2024

Total time taken to generate the page: 0.00726 seconds