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Home » RBC Forums » General Discussion » SDC_68k (The smallest possible DIL64 MC68000/68010 computer, CP/M capable)
SDC_68k [message #5907] Sat, 02 February 2019 03:44 Go to next message
gbm is currently offline  gbm
Messages: 19
Registered: January 2018
Junior Member
SDC_68k
- the smallest possible DIL64 MC68000/68010-based computer by gbm

Features:
• footprint: MC68000 DIL64 socket
• hardware monitor with single-stepping, disassembly, memory editing and drag-and-drop HEX file loading
• 256/512 KiB RAM, 64 KiB ISP Flash
• terminal (console) interface with interrupt capability
• timer with interrupt
• diskette emulation in Flash memory for CP/M-68k support
• on-off or PWM-controlled RGB LED
• user button
• Power supply, h/w monitor communication and target computer terminal via USB double VCOM device
• whole computer logic other than the CPU implemented in STM32L496 or L4R5 microcontroller


Software needed on PC side: a terminal emulator program (TeraTerm 4.101 or newer is recommended).

Top view:
index.php?t=getfile&id=1247&private=0
Bottom view:
index.php?t=getfile&id=1249&private=0
  • Attachment: sdc68ktop.jpg
    (Size: 108.25KB, Downloaded 430 times)
  • Attachment: sdc68kbot.jpg
    (Size: 146.67KB, Downloaded 434 times)

[Updated on: Sat, 02 February 2019 03:50]

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Re: SDC_68k [message #5908 is a reply to message #5907] Sat, 02 February 2019 03:59 Go to previous messageGo to next message
just4fun is currently offline  just4fun
Messages: 97
Registered: May 2017
Location: Dark side of the Moon
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Wow!... Great! Shocked

I see that you are using the internal OSC... Is IC4 a SPI eeprom?

BTW: What STM32 IDE are you using...?
Re: SDC_68k [message #5909 is a reply to message #5908] Sat, 02 February 2019 04:11 Go to previous messageGo to next message
gbm is currently offline  gbm
Messages: 19
Registered: January 2018
Junior Member
Newer L4 models may sync internal osc to USB, so no crystal is necessary.
Yes, IC4 may be QSPI Flash for a bigger disk emulation.
Depending on binary size I use Keil or Atollic. So far Keil is enough (< 32 KiB).
Re: SDC_68k [message #5911 is a reply to message #5909] Sat, 02 February 2019 07:23 Go to previous messageGo to next message
mikemac is currently offline  mikemac
Messages: 168
Registered: March 2017
Senior Member
Interesting board! Are you going to share any of the design files, codes, etc? What's the fastest 68K do you think the STM32L4 can reasonably support?


Mike
Re: SDC_68k [message #5913 is a reply to message #5911] Sat, 02 February 2019 10:29 Go to previous messageGo to next message
gbm is currently offline  gbm
Messages: 19
Registered: January 2018
Junior Member
As I wrote earlier in the threads describing other SDC variations:
- SDC was designed mainly for hardware monitoring, CPU exercising and for showing the operation of a computer at a very low level, not for performance or personal computer use. With MC68000 at 5 MHz, the first, experimental firmware version runs at 305 k bus cycles per second - equivalent to merely 1.2 MHz with 0WS. I run OSes on SDC for fun and for proving that it's a real computer. Still, the CP/M runs quite fast because of very fast mass storage access. I could probably get 3x better CPU performance giving up all the monitoring stuff. With SDC_68k, one may see the prefetch mechanism, exception handling, the famous MC68010 loop mode and several other interesting things. Every bus cycle is handled via an interrupt on STM32, so the interrupt frequency is quite impressive.
- As of today, I may share the schematics, PCB designs, binaries and software ideas (including the CPU and peripheral engine in source form). The rest, particularly the USB stuff, is closed-source.

Processors supported so far by various SDC models are: Z80, 8080, 8085, 65C02, W65C816, MC68008 and MC68000/68010. 8088/8086 and 8008 are in the works.
There are also two SDC designs that may be assembled in 30 minutes with just a BluePill board, a breadboard and 65C02 or 8085 CPU. The cost of components for these is around 7 USD.

MC68010 loop mode in action, viewed with SDC hardware monitor:
index.php?t=getfile&id=1252&private=0
  • Attachment: 68010loop.png
    (Size: 16.39KB, Downloaded 373 times)

[Updated on: Sat, 02 February 2019 10:37]

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Re: SDC_68k [message #5915 is a reply to message #5913] Sat, 02 February 2019 15:43 Go to previous messageGo to next message
mikemac is currently offline  mikemac
Messages: 168
Registered: March 2017
Senior Member
Thanks for the info. I was curious as to the software techniques you were using in the STM32 to interface to the external MCU's signals. I keep thinking about something similar for a 16MHz 68K and I can't decide if I should use a FPGA or a micro. In my case, I'd use a 240MHz Renesas S7G2 if I went the micro route. I'm more familiar with it than the STM32 family. And the Nordic nRF52840 probably doesn't have enough pins besides being too slow for this application.


Mike

[Updated on: Sat, 02 February 2019 15:44]

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Re: SDC_68k [message #5916 is a reply to message #5915] Sun, 03 February 2019 02:23 Go to previous messageGo to next message
gbm is currently offline  gbm
Messages: 19
Registered: January 2018
Junior Member
There are two aspects of "performance" in SDC. First, the hardware must guarantee the proper operation of a microprocessor. Second, we want the computer to be fast. ;)
With computer's logic being implemented completely with a microcontroller, to provide the correct bus operation we must observe two timing-critical conditions:
- tristating the bus at the end of a read cycle,
- deasserting READY/DTACK or asserting WAIT before/when the bus cycle starts.
The above cannot be done in firmware. The obvious solution is to use simple logic ICs or an FPGA. We took the hard way and implemented this using DMA in a microcontroller, so not even a single gate nor a flip-flop was needed. Without hardware DMA that could not be achieved even with a 400 MHz micro. In SDC all the signals of a CPU are simply connected to a microcontroller. Of course, the faster the micro, the better operational performance may be achieved. We used STML4 series at 80 MHz because the faster F4, F7 and H7 (400 MHz) series have much less flexible DMA module, which would not provide the functionality needed in the SDC.

To make a small and fast *modern* ;) retrocomputer, FPGA is a way to go. To make a tiny, flexible, controllable, redefineable and monitorable one - SDC idea is better. The peripherals, interrupt logic and hardware monitor are implemented in firmware and may be easily modified. The hardware monitor console must be implemented in software to provide status display, command interface, disassembly, run control, .hex loading, etc. - you would need a soft-core in an FPGA to do that (that's possible of course).

5-Volt logic compatibility is another story - easy with a uC, not sure if available at all in a modern FPGA.

The real fun is to make a keychain-sized computer fitting under the CPU, like SDC_68k and SDC_8085. For me, it's not only an useful educational toy (you cannot show the bus-level operation of an ARM micro with a debug probe, just instruction-level; no problem with an old micro in an SDC) but also a teaser for students - "see what you can do with a good, modern microcontroller".

[Updated on: Sun, 03 February 2019 02:23]

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Re: SDC_68k [message #6190 is a reply to message #5916] Mon, 25 March 2019 10:54 Go to previous message
denis2342 is currently offline  denis2342
Messages: 11
Registered: February 2017
Junior Member
Hi

Over the last years I played a lot with MC68000 and MC68010 connected to a Arduino Mega with breadboard cables.
This year I switched to a PCB.

/forum/index.php?t=getfile&id=1305&private=0

Here I repeated the loop from the screenshot above:

/forum/index.php?t=getfile&id=1306&private=0

You can the see Function Code switches from Supervisor Program to Supervisor Data, you can
clearly see the READs and WRITEs. You can see UDS/LDS and the Interupt.

No disassembler yet, no OS, everything needs to be put in by hand. Except the Memory
from 0x0000 to 0x1000 is simulated by the ATMega. But I have cycle exact timings with
which I found several errors in the original Motorola documentation.

The Controlcode can also handle Bus Errors (the hardware signal) and Interrupts.

Denis

[Updated on: Mon, 25 March 2019 10:55]

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