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8080 varieties - differences [message #5877] Fri, 25 January 2019 00:46 Go to next message
gbm is currently offline  gbm
Messages: 19
Registered: January 2018
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During my trials of SDC_One 8080 versions I discovered something not mentioned in the tech docs (at least in the ones I could find on the net).
I currently have 5 different 8080s and I wait for the AM9080 I ordered from eBay to arrive, to be able to verify the famous AC flag difference.
Two of the chips, namely Romanian (?Wink MMN8080 and Russian KP580BM80A have a "feature" related to interrupt handling, which looks like a hardware bug.

During an INTA cycle, if the instruction forced on the bus is CALL (not single-byte RST), the CPU generates more read cycles to fetch the rest of instruction (CALL target address).
Intel 8080A (as well as MCY7880 and one more unnamed 8080) send status byte of 0x02 during these cycles (not documented in basic Intel docs, but quite logical), while, if the interrupt request is not deactivated during the first INTA cycle, the Russian and Romanian clones send 0x03 - quite strange. Then things get worse. If the request remains active after all 3 bytes of CALL are injected, during stacking the PC status byte value is 0x05, and immediately after stacking the PC, the CPU repeats INTA and PC stacking, effectively entering the microcode loop (and wrapping the stack around, overwriting the memory) until the IRQ is deactivated.

For these 8080 clones to work correctly, interrupt request MUST be deactivated during the initial INTA cycle.
The Intel docs suggest to deactivate IRQ during INTA but don't say that it's obligatory to do this. A reasonable CPU should operate normally with interrupt request being constantly active. The mentioned 8080 clones seems not to clear the internal interrupt enable during INTA cycle, although the INTE status output actually goes low as it should.

[Updated on: Fri, 25 January 2019 00:48]

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Re: 8080 varieties - differences [message #5879 is a reply to message #5877] Sat, 26 January 2019 12:23 Go to previous messageGo to next message
etchedpixels is currently offline  etchedpixels
Messages: 194
Registered: October 2015
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The Soviet chips were reverse engineered so I wouldn't be surprised if a totally weird feature nobody ever used was slightly wrong. The soviet Z80 clones also have a few obscure corner cases broken.

There are some other differences too depending upon the era including the speed (to 3MHz). The final versions (KR580VM1) could run on 5v only, had extra instructions Intel never did and clocked up to about 5MHz.


Alan
Re: 8080 varieties - differences [message #5891 is a reply to message #5879] Wed, 30 January 2019 10:37 Go to previous messageGo to next message
Sergey is currently offline  Sergey
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Registered: October 2015
Location: Portland, OR
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That is pretty weird. First of all, I am not quite clear about the status word. It looks that 8080 should send 0x23 status word during the interrupt acknowledge cycle (see page 2-6 here).
Next, I am 99.9% sure that clones work correctly with 8259 PIC, which does exactly what you've described: It keeps the INT line active until it receives 3 interrupt acknowledge pulses, allowing it to feed CALL instruction to the CPU. This effectively results in INT line being active for 3 consecutive bus cycles.
So perhaps there is an issue in the way you do the status word decoding?

[Updated on: Wed, 30 January 2019 10:44]

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Re: 8080 varieties - differences [message #5894 is a reply to message #5877] Wed, 30 January 2019 11:29 Go to previous messageGo to next message
gbm is currently offline  gbm
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Registered: January 2018
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It's not the matter of decoding the status word - I have the access to the actual value of status word.

Soviet & Romanian 8080 behave exactly like Intel/CEMI when RST opcode is jammed in during INTA - no problems there.
If you jam in CALL opcode, there is the next INTA cycle which doesn't look like INTA - Intel&CEMI fetch the CALL address with status code 0x02, which is quite logical but not documented. Soviet&Romanian ones send the code 0x03. INTE output is low (correct) but it lies. After fetching two bytes of CALL address, the CPU generates two PUSH cycles with weird status 0x05, then it repeats the same INTA sequence endlessly, with stach pushes overwriting the memory! This looks like a microcode loop. I don't know the exact behavior of 8259 but I assume it deactivates INT as soon as it gets INTA - with such behavior KP580BM80A would not show its weirdness.

I have verified this several times and I wrote the interrupt controller emulation part of SDC and the proper testing software on 8080 to catch the difference between two breeds of CPUs. Look at the picture below. The first two letters reflect cycle type: IA - INTA, SW - stack write, IN - next byte fetch after INTA with 02 type, In - same with 03 type, Sw - stack push with 05 type. The dot after cycle type means INTE high. OUT 79 causes the interrupt request.

Bad INTA behavior - KP580BM80A - with INT input active, the CPU never enters the ISR.
index.php?t=getfile&id=1242&private=0

Same on Intel 8080A /CEMI MCY7880 - correct entry to an ISR
index.php?t=getfile&id=1243&private=0

[Updated on: Wed, 30 January 2019 11:32]

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Re: 8080 varieties - differences [message #5895 is a reply to message #5894] Wed, 30 January 2019 14:17 Go to previous messageGo to next message
Sergey is currently offline  Sergey
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Registered: October 2015
Location: Portland, OR
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Ah, it looks that 8228 System Controller is responsible for generating multiple INTA's for multi-byte interrupt instructions e.g. CALL.
From the 8228 datasheet:
"The devices also generate an Interrupt Acknowledge (INTA) control signal for each byte of a multibyte CALL instruction when an interrupt is acknowledged by the 8080A. This feature permits the use of a multilevel priority interrupt structure in large, interrupt-driven systems."
Re: 8080 varieties - differences [message #5896 is a reply to message #5895] Wed, 30 January 2019 14:57 Go to previous messageGo to next message
gbm is currently offline  gbm
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8228 just generates several INTA strobes, presumably it does this if either INTA or memory read bit is set in a status word. In SDC, I don't generate any INTA strobe, but instead I provide the proper interrupt response in my firmware, based on latched status word value. The problem is, the KP580BM80A will not execute an instruction at CALL target because it is stuck in INTA microcode loop until INT is deasserted. I assume that 8259 deasserts INT to 8080 when it gets the first INTA strobe - that would explain why KP580BM80A may work correctly in a typical computer. I mimicked this in my firmware so it works ok now. The examples above show what happens if my workaround is turned off (which I can do either from h/w monitor console or by writing to IO port by 8080) - then INT is not deasserted and KP580BM80A cannot process an interrupt correctly.
When the workaround is turned on and 03 status word is detected, my interrupt controller code deasserts INT and sets a bit on a special status register, readable by 8080 as input port. This way a smart program running on an 8080 may identify if it runs on Intel-like or KP580BM80A-like CPU. I am curious about the behavior of AMD9080, which is not an exact copy of 8080. Hope I will get it soon.

[Updated on: Wed, 30 January 2019 14:59]

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Re: 8080 varieties - differences [message #5897 is a reply to message #5896] Wed, 30 January 2019 16:29 Go to previous messageGo to next message
Sergey is currently offline  Sergey
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Registered: October 2015
Location: Portland, OR
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Yes, it appears that 8228 actually checks what instruction is being read by the CPU during the interrupt acknowledge cycle. And if it is a CALL instruction, it would generate two more interrupt acknowledge cycles (activate /INTA and keep /MEMR inactive, despite that CPU status word specifies "memory read"). That would ensure that memory remains disconnected from the data bus while the PIC sends out the CALL instruction, and also it allows synchronization of several PICs in cascade configuration.
From 8259A datasheet it seems that it deactivates INT at the same time it deactivates /INTA for the third time (see the /INTA sequence on the last page here). Can you check that KP580BM80A would still work properly if INT is only asserted for three bus cycles? (In which case, it might be not a bug, but a "feature", that would allow operating KP580BM80A with 8259A/KP580BH59, but without 8228/KP580BK28)

[Updated on: Wed, 30 January 2019 16:32]

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Re: 8080 varieties - differences [message #5899 is a reply to message #5897] Thu, 31 January 2019 01:42 Go to previous messageGo to next message
gbm is currently offline  gbm
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I don't think that 8228 knows anything about an instruction jammed during INTA. It's simpler than that - during CALL address fetch 8080 generates control word with ONLY memory read bit set (02), and this value (as well as 03 emitted by KP580BM80A) causes the 8228 to repeat INTA strobe.

As I wrote previously - the problem does not appear with RST instruction - INT kept active does not affect the correct interrupt procesing.

I modified SDC firmware to deactivate INT during the last byte of INTA response (to mimic 8259A behavior but only if CPU still sends INTA bit in the status word). As you can see below, two irregular cycles are generated ("In" cycle type = 03), then two PUSHes with 04 status, so 8259A successfully corrects the problem.

At least I had fun of finding something really interesting with SDC_One, which could probably be never found with a "normal" computer. ;)

KP580BM80A - INT deactivated while jamming-in the last byte of CALL instruction - no problem in this case.
index.php?t=getfile&id=1244&private=0
Re: 8080 varieties - differences [message #5902 is a reply to message #5899] Thu, 31 January 2019 13:11 Go to previous messageGo to next message
Sergey is currently offline  Sergey
Messages: 120
Registered: October 2015
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Yes, quite possible that 8228 looks for INTA cycle, followed by memory read as it would be the case with CALL (vs. INTA followed by stack write as it would be the case with RST), and mimics INTA cycles in this case.
Anyway if used with 8228, it seems that the soviet KP580BM80A would behave the same as the original Intel 8080A.

Good experiments and the discussion!
Re: 8080 varieties - differences [message #5903 is a reply to message #5902] Thu, 31 January 2019 13:50 Go to previous messageGo to next message
gbm is currently offline  gbm
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Wrong: 8228 has not too much to do with that. KP580BM80A behave like Intel when used with 8259A, cause it's 8259A who deasserts INT line during the last byte of CALL jammed-in during INTA. Without that deassertion the CPU enters microcode loop. The problem does not lie in the strange status codes sent by KP580BM80A; these status codes only show the problem, and the problem is: KP580BM80A does not disable interrupts internally when it should. Any reasonable CPU should be happy with interrupt request continuously asserted, the KP580BM80A is not.
However if RST, not CALL is used for ISR entry, the KP580BM80A may have INT continuously asserted and it doesnt't enter the microcode loop. That's really strange.
Re: 8080 varieties - differences [message #5904 is a reply to message #5903] Thu, 31 January 2019 14:54 Go to previous messageGo to next message
Sergey is currently offline  Sergey
Messages: 120
Registered: October 2015
Location: Portland, OR
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Yes, correction, what I've meant is "if used with 8259A, KP580BM80A would behave the same as 8080A (also with 8259A)"

I do understand that KP580BM80A will enter a microcode loop if INT is held down for more than 3 bus cycles, AND if the instruction it gets during INTA cycle is CALL. Yet, what are the chances of that happening in a system without 8259A? I'd assume such systems would normally use RST instructions for the interrupts.

I am curious whether Czech's Tesla MHB8080A is similar to 8080A or to KP580BM80A?

<rant>
There is no such thing as "Reasonable CPU" Smile Most CPUs I know are unreasonable.
Perhaps Z80 is the most reasonable of them all. Except of:
  1. Strange voltage level requirements on CLK input
  2. No hysteresis on /RESET pin, and so an external Schmitt trigger is needed to implement a proper reset
  3. /M1 pin - why not /INTA instead?
  4. (Not quite Zilog's fault) but good luck with integrating Z80 CPU with 8259A PIC or 8257/8237 DMAC
</rant>
Re: 8080 varieties - differences [message #5905 is a reply to message #5904] Fri, 01 February 2019 00:26 Go to previous message
gbm is currently offline  gbm
Messages: 19
Registered: January 2018
Junior Member
I think this behavior of interrupt handling has its roots in the primitive concept of 8008. Maybe (just my speculation) KP580BM80A mimics the behavior of 8080 without 'A' letter, about which we know almost nothing. RST was originally intended as the only reasonable interrupt response. CALL look like a later concept.

Any *reasonable* processor should be happy to work with interrupt request constantly active. It should enter the interrupt service, execute the ISR, finish it and enter the interrupt service again. This is how every CPU (other than 8008 and KP580BM80A with CALL) behaves with respect to maskable interrupts. KP580BM80A somehow treats INT as non-maskable in this special case. Another story is what happens (if anything) between those two ISRs. Most CPUs execute one instruction of a thread code (AVR, x86), some not (8080, ARM Cortex). Actually the behavior of ARM Cortex and 8080 is the correct one, as ISR has always higher priority than thread.

As of Z80: M1 is quite useful - note that 8080 also has M1 status bit, only 8228 doesn't output it. It's easy to generate INTA based on M1, but not the reverse.
Z80 outputs ordinary memory read for CALL address fetch after INTA. I know of some designs where 8259A was used with Z80 - it required just two flip-flops and some gates.

The SDC_One may work with Z80 in all three interrupt modes. The interrupt controller software in SDC works the same for 8080, 8085, Z80, MC68008 and 65C02; it does not even differentiate between 8080 mode and Z80 native mode - it has fully programmable response to INTA and may supply from 1 to 3 bytes during the first INTA and one or two subsequent cycles. That's the advantage of a software-defined computer over hardware design. ;)
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