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| Re: pdp-10 fpga [message #6636 is a reply to message #6474] |
Mon, 07 October 2019 18:48   |
robg
Messages: 43
Registered: October 2017
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Well, it time for an update on this. I've got all of the hardware basically working. I can successfully telnet into the board via its network interface (see last screenshot), and the serial console works fine. So the FPGA clocking, RAM, Serial ROM and IDE/CF interface all checkout. The only Verilog I've changed is around generating the clocks from the 50 MHz oscillator on the FPGA board.
The DS1337 RTC chip seems to work from a hardware perspective in that I can write to it, read those values from it, and see that the values stored are retained across a power-cycle via battery. But I don't understand the values that ITS is writing to it, and ITS does not seem to read from it at boot time, so I have to manually set the time on a reboot.
On the network side, I can't telnet out (at least) because the TELNET binary is missing on the disk image I have, and some of the CHAOSNET stuff that Conroy shows on his screenshots on his writeup does not work for me. But I don't think these are hardware problems, but rather software ones and/or my lackof understanding how to get them to work.
Also for reasons as yet unknown the usual ITS shutdown sequence does not work.
I made a few hardware blunders on this prototype, so I'm doing another spin of the board, while making some changes to make it usable as a Multicomp system also (adding an SD card interface for sure, maybe VGA and PS/2 by reusing the pins of Ethernet interface that aren't usable in a Multicomp system).
Once I get this next iteration of the board debugged, I'll post the schematics, KiCad files, etc. on a builderpage.
Conroy has a few screenshots on his writeup as he debugged his original board. Here are some of the equivalent screenshots for my version of the board.
Initial boot, zeroing out and displaying some memory. This shows basic PDP10 instructions running to get to this point.
Depositing some code via the ROM monitor, then running it.
Booting Conroy's customized version of the Incompatiable Timesharing System (ITS).
A directory listing.
Telneting in the board, logging in, checking the time, listing some files, and running ":peek", which is like Unix's top or ps. It shows me logged in as "ROBG" on the console, and "ROBG2" via the network.
Rob
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| Re: pdp-10 fpga [message #8080 is a reply to message #6922] |
Wed, 11 November 2020 09:14 |
gerryk
Messages: 16
Registered: February 2017
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I git a board for this project from Rob back in February, and between COVID related delays and various other impediments, it has taken me until now to get it done. I have 99% of the board done, with only the crystal for the RTC and the ethernet adapter remaining to fit, and they are in the mail, so I'm rapidly approaching the point of initial power-up.
Has anyone else tried this project, whether on Rob's board or their own?
I do have a couple of questions...,
1. Is there a bitstream that I can just blast onto the FPGA, or do I need to download Quartus or something to synth it from the VHDL?
2. Is there an image with Conroy's ITS I can just image to the CF card? I can see what looks like the files for ITS, but I doubt the PDP10 can understand FAT32, so I guess I need an image of a PDP10 disk, right?
Any help gratefully received.
This is the board, BTW...
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| Re: pdp-10 fpga [message #8081 is a reply to message #8080] |
Wed, 11 November 2020 19:49 |
robg
Messages: 43
Registered: October 2017
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Member |
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gerryk wrote on Wed, 11 November 2020 09:14I git a board for this project from Rob back in February, and between COVID related delays and various other impediments, it has taken me until now to get it done. I have 99% of the board done, with only the crystal for the RTC and the ethernet adapter remaining to fit, and they are in the mail, so I'm rapidly approaching the point of initial power-up.
Has anyone else tried this project, whether on Rob's board or their own?
I do have a couple of questions...,
1. Is there a bitstream that I can just blast onto the FPGA, or do I need to download Quartus or something to synth it from the VHDL?
2. Is there an image with Conroy's ITS I can just image to the CF card? I can see what looks like the files for ITS, but I doubt the PDP10 can understand FAT32, so I guess I need an image of a PDP10 disk, right?
Any help gratefully received.
This is the board, BTW...
Hi Gerry,
You're the only person I sent a board to. I've since reworked to the board to use a Spartan-6 FPGA board. The Spartan-6 is not only larger, allowing for more system possibilities, it is cheaper too. I've almost got the revised board ready for anyone who might be interested.
Anyway, I'll continue to support your use of the Spartan-3E version. Answers to your questions:
1. I've attached a dump of the serial ROM used with the board. This binary file contains the FPGA bitstream and the 1K-word PDP10/X ROM image. Just burn this to the W25Q32JV and you should boot into the ROM monitor immediately on power-up.
2. The archive hosted by this site at http://www.retrobrewcomputers.org/fpga-pdp10-archive/v3arch. zip contains the necessary disk image at v3arch/disk/sim10x.disk. Write that to your Compact Flash card.
Let me know if you have more questions...
Rob
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| Re: pdp-10 fpga [message #8094 is a reply to message #8093] |
Mon, 16 November 2020 21:37 |
robg
Messages: 43
Registered: October 2017
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Member |
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Hi Harris,
I hope to update the files for the Spartan-6 version in the next couple of weeks. It won't be on the Wiki, probably GitHub instead, as I can't reset my wiki password with the forum email not working. The stuff I have on my builderpage is for the Spartan-3 version, frozen in time.
I'm not sure exactly what you mean by "ability to multiboot," but the board can run both Multicomp and PDP10/X, though switching between them is a manual process of using the Xilinx ISE/iMpact tool to program the FPGA or serial ROM each time you want to switch. And as a bonus  because the QMTECH FPGA board I'm using has SDRAM, the system will run Will Sowerbutt's socZ80, which Alan Cox once referred to as one of the fastest non-software-emulated Z80 system he's used.
And yep, I'm in Austin, on the southwest side. Howdy neighbor.
-- Rob
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| Re: pdp-10 fpga [message #8416 is a reply to message #8413] |
Fri, 26 March 2021 21:27 |
robg
Messages: 43
Registered: October 2017
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Member |
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gerryk wrote on Fri, 26 March 2021 03:09robg wrote on Wed, 11 November 2020 19:49
1. I've attached a dump of the serial ROM used with the board. This binary file contains the FPGA bitstream and the 1K-word PDP10/X ROM image. Just burn this to the W25Q32JV and you should boot into the ROM monitor immediately on power-up.
Hi Rob
Got a little sidetracked over the last few months, but finally got round to trying this. I hvae an SPI EPROM flashed with the attached image (and verified by reading off and diffing against the original binary). The FPGA starts up with the default LED flashing image, but that's as far as it goes.
If I connect a serial terminal to the TTY, I just get a series of NULLs.
I have traced the SPI lines from the EPROM to the FPGA headers, and all seems fine.
I guess I am missing something obvious but can't think what it might be.
Hi Gerry,
In that November message, I incorrectly suggested that the Spartan-3 FPGA configuration is loaded from the SPI ROM on the system board, but that's not right. On the Spartan-3 version you have, the SPI ROM on the system board provides the PDP10/X boot code, while there's a separate ROM on the FPGA daughterboard that provides the FPGA bitstream. So you''ll need to use the Xilinx ISE tools to program the FPGA. I'll need to send you a bitstream. (On the Spartan-6 version, it is the case that there's one ROM that stores the FPGA config and the PDP10/X boot code.)
-- Rob
[Updated on: Sat, 27 March 2021 06:42] Report message to a moderator |
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| Re: pdp-10 fpga [message #8426 is a reply to message #5326] |
Mon, 29 March 2021 22:03 |
robg
Messages: 43
Registered: October 2017
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Member |
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Ok, let's simplify things a bit. I've attached 'kx_bram.bit' which is the PDP-10/X bitstream that doesn't use the config ROM nor the SPI ROM. The Xilinx tool will write this via JTAG to the FPGA's SRAM. Note, in this mode, the FPGA will forget the bitstream when the power is off.
After you program this into the FPGA, you should see something on the serial port (set to 9600 baud 8N1). Hopefully you'll see
Before doing this, you might find it helpful to reprogram the FPGA config ROM with the default LED demo bitsteam, which I've also attached. I find this useful to easily tell the difference between a default bitstream and a programmed bitstream.
If load 'kx_bram.bit' works, then you can load 'kx_bram.mcs' also attached, into the FPGA config ROM. Program the ROM, turn off the board, then turn it back on. You should see the same serial port output. If that works, that will be the permanent bitstream for the board. The SPI ROM will no longer be used at all.
Let me know how it goes...
-- Rob
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[Updated on: Mon, 29 March 2021 22:05] Report message to a moderator |
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. I have some other possible targets, like a DE0-Nano and a DE10-Lite, but they are Altera-based boards. 
