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pdp-10 fpga [message #5326] Mon, 15 October 2018 09:23 Go to next message
bob98033_yahoo.com is currently offline  bob98033_yahoo.com
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I did an inquiry with Mr. Conway if he would release the pc artwork and rom file for his PDP-10 fpga running MIT's ITS (Incompatible Timeshare System). Well not only did he send the files he sent me a set of PC blank boards ready to be stuffed! I attached the PC artwork files and ROM binary file. The ROM file is the motorola S3 format as the bin hex format is to large for some rom burner's. Note this FPGA implementation is different from other pdp fpga implementation in that it doesn't use a development board. The reason for that is the 36 bit memory. If access to 36 bit was remapped to fit in 32 bit memory the performance would be terrible. Instead five 512kbyte static rams were used to make 512k X 40 memory ( the four most significant bits always low to get 36 bits). There is no Jtag interface. Instead development was done on MAC OSX making a binary image including the code to program the FPGA plus a console program written in PDP-10 assembly. The router files are not in gerber format but in ExpressPCB format. ExpressPCB can convert the file format to gerber format for an additional cost $60 per PCB order. This project uses two PCB so two orders ($120 to convert to gerber format). I have no idea how many people would want a pdp-10 so the conversion to gerber format may not happen.

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Re: pdp-10 fpga [message #5328 is a reply to message #5326] Mon, 15 October 2018 11:07 Go to previous messageGo to next message
gkaufman is currently offline  gkaufman
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I may be able to convert the files at no cost. I'll try tonight.

- Gary

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Re: pdp-10 fpga [message #5329 is a reply to message #5328] Mon, 15 October 2018 11:12 Go to previous messageGo to next message
gkaufman is currently offline  gkaufman
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Try these two...

- Gary

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Re: pdp-10 fpga [message #5332 is a reply to message #5326] Mon, 15 October 2018 12:39 Go to previous messageGo to next message
zamp is currently offline  zamp
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bob98033_yahoo.com wrote on Mon, 15 October 2018 12:23
I did an inquiry with Mr. Conway if he would release the pc artwork and rom file for his PDP-10 fpga running MIT's ITS (Incompatible Timeshare System).


Is this David Conroy's FPGA PDP-10? The only real writeup I've seen on it is at http://www.fpgaretrocomputing.org/pdp10x/.

Have you come across any additional information on this FPGA PDP-10? Unless there have been new developments, David was running a version of ITS that he had to modify to use the disk-on-module and serial interfaces that he was using in his PDP-10 clone. Do you know if David has shared his changes to ITS that let it work with his clone?

The idea of building a PDP-10 clone is pretty interesting. If an OS to run on it was available, I'd probably want to build one.

Ron

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Re: pdp-10 fpga [message #5333 is a reply to message #5332] Mon, 15 October 2018 14:54 Go to previous messageGo to next message
bob98033_yahoo.com is currently offline  bob98033_yahoo.com
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I asked David about how to get an image of the OS installed and he sent me on a DVD a copy of the entire pdp-10 development directory from his MAC OSX computer. It includes the source code for the fpga,assembly code for the console,tools to make the ROM image in both motorola S3 and bin hex format, device drivers for aha disk driver,realtime clock,network driver (CHAOS Net the "original arpanet code") and bunch of tools including a special custom emulator that duplicates the functionality of fpga. The last tool he created because there is no FPGA development board and no board debugger. Basically the software development cycle is write source code,compile it,flash result to ROM,plug flash rom into board and turn on the power! His solution is to create an emulator of the FPGA. Right now the tools are written for MAC OSX The DVD does include binary images of flash rom and OS as documented on his site. We can definitely have a PDP-10 running MIT ITS system now... If we wish to modify things then we should update the development environment to run on Linux and windows. Right now I wondering how I should upload the DVD. It is hundreds of megs of source and binary code.

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Re: pdp-10 fpga [message #5334 is a reply to message #5333] Mon, 15 October 2018 17:33 Go to previous messageGo to next message
tingo is currently offline  tingo
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Very interesting. Doesn't Xilinx FPGAs have a JTAG interface "built in" to the chip? If so, it wouldn't be hard (well, not too hard) create / wire up a new board and get the bitstream working on that.
Please find a way to put at least source code online (Github / Gitlab repository?Wink, if at all possible.

Torfinn

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Re: pdp-10 fpga [message #5335 is a reply to message #5334] Mon, 15 October 2018 19:56 Go to previous messageGo to next message
Andrew B is currently offline  Andrew B
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Hey all - this sounds like fun, feel free to use the wiki here to collect up information. Let me know if you need help creating a page.

As far as the files, if you want I can create a temporary FTP login for you to upload to and then make the contents available as a folder on the domain here, similar to the legacy wiki archive. We can also do a .zipped version if anyone wants to the grab all of it at once.

Github probably makes a lot of sense for new versions going forward, but best to have a copy stashed here as well.

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Re: pdp-10 fpga [message #5337 is a reply to message #5334] Mon, 15 October 2018 21:22 Go to previous messageGo to next message
bob98033_yahoo.com is currently offline  bob98033_yahoo.com
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Well right now the three lines for jtag interface are connected to the serial flash rom chip to program the fpga on "reset". The fpga after it is configured then toggles the jtag lines to load the console code from the flash rom to ram (I think high-memory)to start the console/monitor program.

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Re: pdp-10 fpga [message #5338 is a reply to message #5335] Mon, 15 October 2018 21:44 Go to previous messageGo to next message
bob98033_yahoo.com is currently offline  bob98033_yahoo.com
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I just zipped up the contents of the DVD. The file size is 400 megs since it contains source and binary for everything including a complete ITS file system. I just need a spot to upload it to.

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Re: pdp-10 fpga [message #5339 is a reply to message #5338] Mon, 15 October 2018 22:10 Go to previous messageGo to next message
Andrew B is currently offline  Andrew B
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I PMed some details, go ahead and upload and I'll get it moved to a suitable location & post a link here.

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Re: pdp-10 fpga [message #5340 is a reply to message #5339] Tue, 16 October 2018 13:25 Go to previous messageGo to next message
will is currently offline  will
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"I have no idea how many people would want a pdp-10"

Well I would!!

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Re: pdp-10 fpga [message #5341 is a reply to message #5329] Tue, 16 October 2018 16:29 Go to previous messageGo to next message
bob98033_yahoo.com is currently offline  bob98033_yahoo.com
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here is the pictures of the two blank PC boards provided by Gary Conway. Someone please compare to gerber files generated by Gary to verify if correct.
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  • Attachment: DSCN0362.JPG
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Re: pdp-10 fpga [message #5342 is a reply to message #5340] Wed, 17 October 2018 02:51 Go to previous messageGo to next message
pbirkel is currently offline  pbirkel
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"I have no idea how many people would want a pdp-10"

I would as well!!

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Re: pdp-10 fpga [message #5345 is a reply to message #5341] Wed, 17 October 2018 10:33 Go to previous messageGo to next message
gkaufman is currently offline  gkaufman
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bob98033_yahoo.com wrote on Tue, 16 October 2018 16:29
here is the pictures of the two blank PC boards provided by Gary Conway. Someone please compare to gerber files generated by Gary to verify if correct.


As long as the original express pcb files are accurate, the converted files should be identical.

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Re: pdp-10 fpga [message #5347 is a reply to message #5345] Wed, 17 October 2018 13:38 Go to previous messageGo to next message
bob98033_yahoo.com is currently offline  bob98033_yahoo.com
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I was comparing the express pcb file conversion to sbc6120 kicad/gerber file and I don't see a Excellon drill file ... *drl. I don't know too much about gerber files is a drill file necessary?

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Re: pdp-10 fpga [message #5348 is a reply to message #5347] Wed, 17 October 2018 15:30 Go to previous messageGo to next message
gkaufman is currently offline  gkaufman
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I'm no expert on Gerber files (by a long shot), but there appears to be a drill file (.xln).
The files appear to load nicely using Gerbv.

I exported the gerbers as configured for OSH Park, but most other vendors should be fine with these files.

- Gary

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Re: pdp-10 fpga [message #5350 is a reply to message #5348] Fri, 19 October 2018 05:28 Go to previous messageGo to next message
bob98033_yahoo.com is currently offline  bob98033_yahoo.com
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gkaufman:
The syspc-11.xln and x3epcb-03.xln report errors when I try to open the files under Gerbv. "Unexpected symbol" is displayed in a dialog box and no layer is drawn...Please check.

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Re: pdp-10 fpga [message #5353 is a reply to message #5350] Fri, 19 October 2018 06:19 Go to previous messageGo to next message
gkaufman is currently offline  gkaufman
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Both open and display fine for me using Version 2.6A of Gerbv.

Extract the .zip into a directory
F)ile, O)pen Layers
browse to the files...
^A to select all
O)pen
you can then uncheck or check each layer to view.

I'll upload to OSHPark in a few minutes and post a link.

- Gary


bob98033_yahoo.com wrote on Fri, 19 October 2018 05:28
gkaufman:
The syspc-11.xln and x3epcb-03.xln report errors when I try to open the files under Gerbv. "Unexpected symbol" is displayed in a dialog box and no layer is drawn...Please check.

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Re: pdp-10 fpga [message #5354 is a reply to message #5353] Fri, 19 October 2018 06:29 Go to previous messageGo to next message
gkaufman is currently offline  gkaufman
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OSHPark links for ordering (fairly costly):

SYSPC-11: https://oshpark.com/shared_projects/CpW7PMc1

X3EPCB-11: https://oshpark.com/shared_projects/X3VYEDr2

- Gary

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Re: pdp-10 fpga [message #5356 is a reply to message #5354] Fri, 19 October 2018 07:21 Go to previous messageGo to next message
Andrew B is currently offline  Andrew B
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The archive file from bob is now available at:
http://www.retrobrewcomputers.org/fpga-pdp10-archive/v3arch.zip

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Re: pdp-10 fpga [message #5360 is a reply to message #5354] Fri, 19 October 2018 10:48 Go to previous messageGo to next message
pbirkel is currently offline  pbirkel
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Said Gary: "OSHPark links for ordering (fairly costly)"

Rahtah! I'd support a group-buy from a (much) more cost-effective supplier. Anyone else here so inclined?

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Re: pdp-10 fpga [message #5365 is a reply to message #5360] Fri, 19 October 2018 23:11 Go to previous messageGo to next message
ale500 is currently offline  ale500
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The FPGA alone is 36 a pop Sad. There are nice Spartan 6 modules (from aliexpress) with a 16 k LE fpga and enough pins for the RAM and IDE, I think. One could use that, the baords are like 17 € or so.

https://de.aliexpress.com/item/Spartan6-entwicklungsboard-XI LINX-FPGA-SDRAM-Spartan-6-tr-gerplatte-XC6SLX16/32851234772. html?spm=a2g0x.search0104.3.9.7c374763DUa5YJ&transAbTest =ae803_4&ws_ab_test=searchweb0_0%2Csearchweb201602_1_103 20_10065_10068_318_10547_319_10548_317_10696_450_10084_10083 _10618_452_535_534_10304_10307_533_10820_532_10821_10302_204 _10843_10059_10884_323_10887_5023911_100031_10319_320_572761 1_321_322_10103_448_449%2Csearchweb201603_45%2CppcSwitch_0&a mp;a mp;algo_pvid=6f30735e-8d64-4bcc-bb1b-1f5bc6bc2632&algo_e xpid=6f30735e-8d64-4bcc-bb1b-1f5bc6bc2632-1

There are two variants one with SDRAM and one with DDR3 DRAM. SDRAM is easier to get to work than DDR3. The only drawback is that the programming is not a standard connector (not a 2x7 2.0 mm header), but a single row od 2.54 mm spaced pins, it works anyways but not all programmers have the flying wires. It could be a possibility.

[Updated on: Fri, 19 October 2018 23:19]

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Re: pdp-10 fpga [message #5366 is a reply to message #5365] Fri, 19 October 2018 23:35 Go to previous messageGo to next message
ale500 is currently offline  ale500
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I did a quick test synthetizing it for a nother FPGA to size the amount of logic needed (Target MachXO2-7000), it needs 108 pins plus one for a LED, the Spartan6 board has 108 free pins plus some leds and pushbuttons.



Design Summary
   Number of registers:   1115 out of  7209 (15%)
      PFU registers:         1022 out of  6864 (15%)
      PIO registers:           93 out of   345 (27%)
   Number of SLICEs:      2721 out of  3432 (79%)
      SLICEs as Logic/ROM:   2310 out of  3432 (67%)
      SLICEs as RAM:          411 out of  2574 (16%)
      SLICEs as Carry:        109 out of  3432 (3%)
   Number of LUT4s:        5173 out of  6864 (75%)
      Number used as logic LUTs:        4133
      Number used as distributed RAM:   822
      Number used as ripple logic:      218
      Number used as shift registers:     0
   Number of PIO sites used: 109 + 4(JTAG) out of 115 (98%)
   Number of block RAMs:  0 out of 26 (0%)
   Number of GSRs:  1 out of 1 (100%)


Looks promising !!!

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Re: pdp-10 fpga [message #5384 is a reply to message #5366] Mon, 22 October 2018 11:26 Go to previous messageGo to next message
bob98033_yahoo.com is currently offline  bob98033_yahoo.com
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Well my first attempt at soldering the 208 pin fpga ended in failure. I had to use "chip quik" to remove the IC. Now of course several of the pins are damaged so I need a new replacement. At $36 a pop I it maybe time to shelf the PDP-10x the project unless you know someone in this forum who has experience soldering SMD of this many pins... 52 pins per side
of one inch length. Notice before I started I got one of the smd "trainer" soldering kit but the IC is only 44 pin flat pack. The pin density of this fpga is much higher than a qfp44 package that comes in the trainer. I have seen "you tube videos" of using a heat gun to solder in a smd chip so maybe that is how you do it. Any suggestions out there ?

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Re: pdp-10 fpga [message #5385 is a reply to message #5384] Mon, 22 October 2018 12:03 Go to previous messageGo to next message
will is currently offline  will
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My recommendation for SMD soldering is always: Use a LOT of liquid flux. Flux and a good soldermask work together and the surface tension of the molten solder allows it to end up where you need it to be. If you have too much solder use solder braid (again with a lot of liquid flux) to remove the excess.

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Re: pdp-10 fpga [message #5386 is a reply to message #5385] Mon, 22 October 2018 13:14 Go to previous messageGo to next message
bob98033_yahoo.com is currently offline  bob98033_yahoo.com
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I forget one detail ... The board I am using from Conway has NO SOLDER MASK. Another item is pad on the board is very short basically the length of the pad on the end IC. What is your suggestion now?

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Re: pdp-10 fpga [message #5387 is a reply to message #5386] Mon, 22 October 2018 14:01 Go to previous messageGo to next message
will is currently offline  will
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Ah maybe the PCB was designed for reflow soldering (you're approaching the limits of my SMD knowledge!). I'm guessing the idea was to put solder paste on the board with a mask or with a syringe, then pop the chip on top, then heat up the whole ensemble.

The PCB doesn't look too horrendously complicated -- maybe you could just make a new version in KiCAD with pads suitable for hand soldering and send it off to a prototyping service which would make boards with a soldermask for you?

[Updated on: Mon, 22 October 2018 14:01]

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Re: pdp-10 fpga [message #5389 is a reply to message #5387] Mon, 22 October 2018 15:38 Go to previous messageGo to next message
jcoffman is currently offline  jcoffman
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My technique for soldering the PQFP-132 386EX went as follows:

A. Coat the PQFP board pads with liquid flux. IMPORTANT.
B. (optional) Tin the board with a flat tip iron with MINIMUM solder. This is not necessary if the HASL layer has enough solder to attach the chip pins.
C. Coat the bottoms of the PQFP pins with liquid flux.
D. Position the PQFP; tack down corners with a DRY (solder-free) flat or wedge tip iron. Re-check positioning constantly.
E. Finish heating all of the pins with the DRY flat or wedge tip iron until all pins pass visual inspection under a jewelers loupe (8X) magnifier.
F. (optional) If you have a low voltage (<3v) tester, buzz out the connections with straight pins used as probes. This is tedious.

--John

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Re: pdp-10 fpga [message #5390 is a reply to message #5389] Tue, 23 October 2018 10:37 Go to previous messageGo to next message
ale500 is currently offline  ale500
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I did solder a QFP208 once, a Spartan2. It was kind of difficult. I did also go for lots of flux, flat tip iron, an solder the corners first. I still have a second Spartan2 that got unused...
I ordered another Spartan6 board, I think it is a better option, the FPGA is already soldered and has 0.1" headers.

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Re: pdp-10 fpga [message #5440 is a reply to message #5390] Wed, 07 November 2018 08:52 Go to previous messageGo to next message
bob98033_yahoo.com is currently offline  bob98033_yahoo.com
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I just ordered a set of ten cpu/system boards from "dirtypcs" for $133. This is much cheaper than OSHPark price of $300 for one set. I chose them because of message of the builders having good luck with "dirtypcs". The vendor is in Hong Kong so I will know in the month if I made a good purchase or not.

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Re: pdp-10 fpga [message #5561 is a reply to message #5440] Tue, 20 November 2018 11:03 Go to previous messageGo to next message
ale500 is currently offline  ale500
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I got today a SDRAM controller in verilog working, at least in the simulator. The pdp10x simulates without problems too. My target will be the Spartan6 on the board I posted about earlier. As soon as something works I'll poste it in the wiki page, maybe we can build something around a cheaper setup. The boards you got (or are going to get are sitting in the states aren't they ?, postage and tax would probably cost as much as ordering new sets from some smart prototypes or similar... I think.

[Updated on: Tue, 20 November 2018 11:04]

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icon7.gif  Re: pdp-10 fpga [message #5679 is a reply to message #5561] Mon, 03 December 2018 22:29 Go to previous messageGo to next message
bob98033_yahoo.com is currently offline  bob98033_yahoo.com
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Today I received from Hong Kong a set of ten cpu/main boards. I also bought six fpga's and six flash spi's. One of the flash IC's is SMD the other five are DIP.
index.php?t=getfile&id=1169&private=0
index.php?t=getfile&id=1170&private=0
index.php?t=getfile&id=1171&private=0
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Re: pdp-10 fpga [message #5688 is a reply to message #5679] Wed, 05 December 2018 06:30 Go to previous messageGo to next message
bob98033_yahoo.com is currently offline  bob98033_yahoo.com
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PDP-10x board inventory:
SYSPC-11 and X3EPCB-11 $20 for the set. SYSPC-11,X3EPCB-11,fpga and flash SPI $40

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Re: pdp-10 fpga [message #5689 is a reply to message #5688] Wed, 05 December 2018 06:57 Go to previous messageGo to next message
pbirkel is currently offline  pbirkel
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bob98033_yahoo.com wrote on Wed, 05 December 2018 06:30
PDP-10x board inventory:
SYSPC-11 and X3EPCB-11 $20 for the set. SYSPC-11,X3EPCB-11,fpga and flash SPI $40


I'm (still) interested in your mini-kit. I'm located in Maryland.

Not looking forwards to soldering the ICs; still a thru-hole guy. Gotta learn sometime I guess ...

THX!

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Re: pdp-10 fpga [message #5944 is a reply to message #5689] Sat, 09 February 2019 08:53 Go to previous messageGo to next message
djmartins is currently offline  djmartins
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I have a MiSTer board and this would make a great core for it!
It already has the MultiComp and a PDP-1 on it and a lot of other cores.
The dev would need to release the FPGA source code though, or write a core for MiSTer.

[Updated on: Sat, 09 February 2019 08:56]

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Re: pdp-10 fpga [message #6437 is a reply to message #5944] Wed, 07 August 2019 05:00 Go to previous messageGo to next message
gerryk is currently offline  gerryk
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I am looking at how feasible this might be. One thing that will definitely need some thought is how to handle the RAM.
RAM on the MISTer is a single SDRAM module... probably 32bit. The RAM for the PDP10/x is 5x512k SRAM modules, set up so that the 40 data bits are provided by the 5 modules directly map to the 36 bits required by the PDP10/x, with the high 4 bits pulled low. This approach would not be possible in the SDRAM module, since there are only 32 data bits, so some code or other translation would be needed to handle the 1 PDP word -> 2 SDRAM word alignment.
Alternatively, a similar SRAM module could be made up to provide the necessary RAM in the same way that Dave Conway has implemented it.

Ok, just saw this:

I got today a SDRAM controller in verilog working, at least in the simulator. The pdp10x simulates without problems too. My target will be the Spartan6 on the board I posted about earlier. As soon as something works I'll poste it in the wiki page, maybe we can build something around a cheaper setup. The boards you got (or are going to get are sitting in the states aren't they ?, postage and tax would probably cost as much as ordering new sets from some smart prototypes or similar... I think.

// Gerry

[Updated on: Wed, 07 August 2019 05:12]

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Re: pdp-10 fpga [message #6438 is a reply to message #5561] Wed, 07 August 2019 05:13 Go to previous messageGo to next message
gerryk is currently offline  gerryk
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ale500 wrote on Tue, 20 November 2018 11:03
I got today a SDRAM controller in verilog working, at least in the simulator. The pdp10x simulates without problems too. My target will be the Spartan6 on the board I posted about earlier. As soon as something works I'll poste it in the wiki page, maybe we can build something around a cheaper setup.
Do you have anything further on this?

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Re: pdp-10 fpga [message #6468 is a reply to message #5326] Wed, 21 August 2019 07:41 Go to previous messageGo to next message
robg is currently offline  robg
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Hello PDP10 Fans,

I've gone down the path of reimplementing Conroy's PDP10/X System Board in Kicad 5. For the FPGA, I'm using a board from Waveshare [1] which uses the same Xilinx Spartan 3E FPGA as Conroy's design. This board uses 2mm pin spacing instead of the usual 2.54mm, but hopefully will be easier to solder than a 0.5mm pitch PQFP. Smile

I've made a few changes as compared to Conroy's original system board:

  • 5V Power via a barrel jack instead of a Molex connector
  • Clocks are derived from the 50 MHz oscillator on the FPGA board instead of using discrete oscillators.
  • TTL (3.3V) serial, removing the MAX232 chips
  • Conroy uses one SPI Serial ROM for both FPGA configuration and the PDP10 ROM. I'm using the ROM on the FPGA board for config only, with a separate SPI ROM on the system board for the PDP10 ROM. This minimizes Verilog changes.
Boards should be arriving in the next couple of days. I'll probably load up a Multicomp system to do basic hardware checkout before tackling Conroy's ITS.

[1] https://www.waveshare.com/product/fpga-tools/xilinx/core/cor e3s500e.htm

-- Rob

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Re: pdp-10 fpga [message #6471 is a reply to message #6468] Thu, 22 August 2019 07:39 Go to previous messageGo to next message
gerryk is currently offline  gerryk
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Very interested to see how this works out Rob.

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Re: pdp-10 fpga [message #6472 is a reply to message #5326] Fri, 23 August 2019 17:55 Go to previous messageGo to previous message
robg is currently offline  robg
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Thanks Gerry.

Well, the boards have arrived, without silkscreen Crying or Very Sad. Guess JLCPCB decided I needed a little bit more challenge when assembling the board. The silkscreen is clearly there on the Gerber viewer on their website, so I guess this is some sort of production mistake.

I've assembled the power circuit (barrel jack, 3.3V regulator, some caps) and added the pin sockets for the FPGA board. Here you can see the FPGA running the little LED demo program that it ships with, so at least it is getting power.

The system board has a couple of LEDs on it, so I will download some Verilog to blink those next.

-- Rob

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