Home » RBC Forums » General Discussion » SDC_One - a contemporary computer with a a real, classic CPU
| SDC_One - a contemporary computer with a a real, classic CPU [message #4206] |
Tue, 30 January 2018 00:18  |
gbm
Messages: 34
Registered: January 2018
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I'd like to present my design of a retrocomputer.
A real, usable computer should have an LED, a button, a terminal and some mass storage. A good, old/style computer should also provide for hardware/level debugging single-stepping through bus cycles, memory and I/O display and editing and memory loading independently from CPU (remember those panels with lamps and switches? .
SDC_One is a software-defined computer based on a real, classic CPU. Other than the CPU, the rest of SDC_One memory, peripherals and glue logic, is implemented with a single Cortex-M4 based microcontroller. The goal of the project was to build a computer which could be used for teaching the basics of computer's operation, hence it provides extensive hardware-level monitoring by single-stepping through bus transfers and instructions, hardware breakpoints, data injection during bus transfers, etc. The peripheral set implemented in SDC_One, including a simple GPIO, console interface and mass storage (diskette emulated in the MCU's Flash) makes it possible to run a real vintage OS, like CP/M.
The computer connects to a PC with a USB cable, providing the power supply and presenting two virtual serial ports to the PC; one is used as hardware monitor interface, the other as target computer's console. A .HEX file may be loaded to the target's memory by dropping it onto the hardware monitor terminal window.
SDC_One consists of an STM Nucleo-L476 board and the daughterboard sitting on top of it, containing the target CPU. The daughterboard contains only the CPU and, an USB connector and some passive components, so the equivalent computer may be easily built with a breadboard instead of daughterboard PCB.
Currently there are four variants of SDC_One, using 8085, Z80CPU, MC68008 and 65C02. The target has 64 KiB RAM and achieves the execution speed of about 400000 bus transfers per second. Z80 and 8085 variants run CPM/80, and MC68008 successfully booted CP/M-68k.
Considering the cost of components and ease of assembly, I suspect that SDC_One may be the most affordable and easiest to assemble retrocomputer.
If anyone is interested, I am ready to share schematics, PCB designs and L476 firmware (currently in binary form only, sources in future).
Also, there is work-in-progress on two other models:
The SDC_Zero cannot run an OS due to it's limited (16KiB) RAM, uses the breadboard and has a total cost of < $6 (sorry, no GPIO other than a single LED and no mass storage at this price, just an option of 48KiB ROM filling the rest of address space).
SDC_68k is a project of an MC68000/010-based computer of the footprint equal to that of MC68000 DIL64 socket, with 256 KiB RAM available to the CPU. No Nucleo board this time.
Both models have the same hardware monitoring capabilities as SDC_One.
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[Updated on: Tue, 30 January 2018 00:21] Report message to a moderator |
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| Re: SDC_One - a contemporary computer with a a real, classic CPU [message #4218 is a reply to message #4207] |
Tue, 30 January 2018 13:28  |
gbm
Messages: 34
Registered: January 2018
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Almost all the pins of L476 are truly 5V-tolerant. Actually, there is only one non-5V pin used for one address line - this may be handled with a Schottky diode and a pullup resistor. I have no problems running 5 V NMOS and CMOS CPUs with L476. CMOS W65C02S and OKI (only) 80C85 are officially specified for 3 V operation. CMOS Z80CPU, officially 5V only, works reliably at 3.3 V with 5 MHz clock.
All the SDC_One daughterboards (except for 5V-only MC68008) are designed for 5/3.3 volt operation - there is a jumper for setting the power voltage.
Also, all the CPUs used so far have TTL-compatible input levels, so they easily accept 3.3 V output levels. Z80CPU clock input may be handled with L476 output set to open drain and 1k5 pullup resistor. There is a place on the PCBs for level-translation gates for clock signal, but so far they were not required. I currently work on 8080 board, on which some logic level translators will be necessary.
[Updated on: Tue, 30 January 2018 13:31] Report message to a moderator |
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| Re: SDC_One - a contemporary computer with a a real, classic CPU [message #4247 is a reply to message #4229] |
Thu, 01 February 2018 14:32 |
gbm
Messages: 34
Registered: January 2018
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MC68008 daughterboard on Nucleo-L476 and another one on Nucleo-L496. The MC68008 board is slightly bigger than the ones with DIL40 CPUs. Also, due to increased number of signals, the RGB LED is connected to an extra connector that may be controlled only by Nucleo-144 board (the bigger one).
The last picture shows MC68008 reset sequence viewed with hardware monitor. Each line contains cycle type id (Supervisor Program Read), adddress and data.
I have finished the design of SDC_68k standalone PCB, having exactly the size of a DIL64 socket. Before ordering the PCB. I need to check the operation of the circuit with Nucleo-144 and a breadboard with MC68000.
[Updated on: Thu, 01 February 2018 14:39] Report message to a moderator |
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| Re: SDC_One - a contemporary computer with a a real, classic CPU [message #5825 is a reply to message #4280] |
Sun, 13 January 2019 12:56 |
gbm
Messages: 34
Registered: January 2018
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Update:
Six versions of SDC_One have been finished so far:
Z80CPU, 80C85, MC68008, 65C02, W65C816S and the newest one - 8080 All the "80" family versions run TinyBASIC annd CP/M-80, 65xx versions run OSI BASIC.
8080 version contains 8080, 8224 and HCT245 level translator - 8228 was not necessary, as the bus cycle info is decoded by STM32.
Two pictures are atached:
SDC_One 8080 with Polish 8080 and 8224 clones
Another one with nice Intel 8080 dated 7726
I have also completed SDC_Zero - a simple SDC with 80C85 or 65C02 using a BluePill board and a common 830-points breadboard, which may be assembled in 30 minutes and costs approx. 7 USD.
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[Updated on: Sun, 13 January 2019 13:03] Report message to a moderator |
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| Re: SDC_One - a contemporary computer with a a real, classic CPU [message #5853 is a reply to message #4206] |
Sun, 20 January 2019 15:31 |
gbm
Messages: 34
Registered: January 2018
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Currently I get 480 kcycles/s with 6502 and ca. 300 kcycles/s with 8080. I plan to redesign the target engine firmware to get better performance. I don't know about the timing of PIC-based stuff, but unless it's PIC32 I guess that's impossible to simulate the microcomputer memory with PIC at 1 MHz. In order to transfer the data, the uC must detect/clock the cycle start, read the address from uP, verify that it's a memory address, output the data, detect (or clock) end of cycle and reverse the bus - 6 actions, each requiring few instructions.
There is no RAM chip in SDC; maybe if the uC is used only for IO and timing, with uP accessing the external RAM, like in Propeddle, that level of performance is possible. SDC implements the whole circuitry of a computer in STM32 firmware, which requires significant work but makes the hardware design and assembly a simple as possible. It took me about 3 hours to assemble and check the 8080 board and 4 hrs to port the SDC firmware to the 8080 target CPU.
SDC was not designed for performance, but rather for monitoring the CPU operation in detail (bus cycle or instruction stepping with bus cycle info display, disassembly and breakpoints). I use it for teaching the basics of computer operation. Still, the performance is not bad. 
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| Re: SDC_One - a contemporary computer with a a real, classic CPU [message #7602 is a reply to message #7537] |
Tue, 05 May 2020 07:34 |
gbm
Messages: 34
Registered: January 2018
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A new (8th) breed of SDC_One is born. I finally got some time to finish the firmware for the 8088/V20 version. As I already had the CP/M-80 running on 8080/8085/Z80 versions, I wrote a minimal stub to switch the V20 into emulation mode and - voila! - got pure CP/M working on a V20. Meanwhile I discovered that in 8080 mode the V20 mimics flag settings of Am9080 rather than those of Intel-style 8080A. And watching the 8080 operation with an instruction queue is a lot of fun.
The current firmware achieves performance equivalent to 1.72 MHz 0WS while clockiong the V20 at 3 MHz.
SDC_One firmware may be easily adopted to support the 16-bit data bus 8086/V30 on the same board. I plan to do it soon. I also plan to write a disassembler module for both operating modes - the current one is for 8080 emulation mode only.
Another news: using an MC6800 version I did some research on undocumented MC6800 instructions and discovered a bunch of these beyond the 7 already known, including a few useful ones. I will post a report soon.
My SDC_One 8080 boards with ceramic Intel C8080A and cerdip Am9080A finally got the period- and origin-correct cerdip D8224 clock chips, while the Polish 8224 equivalents feed the clock signal to Eastern-european 8080A clones. Now, if I could only find the NEC uPD8080A (the original NEC design, not Intel-clone uPD8080AF) for SDC_One 8080... I would trade a few nice chips in ceramic packages for it.
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[Updated on: Tue, 05 May 2020 12:31] Report message to a moderator |
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