Home » RBC Forums » General Discussion » TinyZZ, a Z280 SBC (Exploring Z280)
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Re: TinyZZ, a Z280 SBC [message #4343 is a reply to message #4342] |
Fri, 16 February 2018 12:13   |
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lowen
Messages: 226 Registered: August 2016 Location: Western NC USA
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While I'm going to do my own run eventually, I found results from Stefan Nitschke, who ran dhrystone 1.0 on the CPU280 under the Unix-like UZI280. Here are his numbers:
Benchmarks testing the HiTech Compiler using Dhrystone 1.0 (12.5 MHz) :
z80 Version : 847
z80 Version + z280 Lib : 1041 (22%)
z80 Vers + Optim + z280 lib : 1219 (44%)
For comparison, see the table at http://tech-insider.org/unix/research/1986/0219.html
In a nutshell: The CPU280, with Z280 instructions and 'optimizations' scores in the same general neighborhood as a Sun 2/120, a PDP-11/70, a PC/AT 80286/6MHz PC-DOS 3 system, and many other systems that you'd initially think were far 'better' systems. The CPU280 outscores several runs from VAX-11/750 systems, several PDP 11 systems (11/44, 11/73), and any PC/XT-class systems.
So if you think of the Z280 at 12.5MHz as being the rough equivalent in terms of basic processor speed of the 11/83 or a 10-MHz 68K you'd be in the right ballpark.
I would like to see the 50MHz eZ80 benchmarked, personally. I think everyone would be surprized. The TI-84CE graphing calculator uses a 48MHz eZ80; wonder if there's a C compiler for the beast?
I know that dhrystone is the epitome of the fun to be had with artificial benchmarks, but I am still pleasantly surprized at how well the Z280 holds up against bigger iron, like the 11/70.
--
Bughlt: Sckmud
Shut her down Scotty, she's sucking mud again!
[Updated on: Fri, 16 February 2018 12:14] Report message to a moderator
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Re: TinyZZ, a Z280 SBC [message #4346 is a reply to message #4343] |
Sat, 17 February 2018 05:54   |
etchedpixels
Messages: 333 Registered: October 2015
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There's a whole Zilog toolchain and other supporting stuff. Start with: https://github.com/CE-Programming/toolchain. Nothing open however except in Z80 mode. There were several eZ80 projects but they all seem to have died due to the lack of open information on tools, programmers etc.
There are FPGA alternatives - the T80 core used in Will's socz80 is clock equivalent to the real silicon but will run at 100MHz+ with fast enough RAM or a cache. There's also the Nexgen core which is a modern design executing Z80 instructions and does a lot more at a lower clock rate.
And then of course there's the rabbit ...
[Updated on: Sat, 17 February 2018 05:55] Report message to a moderator
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Re: TinyZZ, a Z280 SBC [message #4347 is a reply to message #4346] |
Sat, 17 February 2018 06:37   |
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lowen
Messages: 226 Registered: August 2016 Location: Western NC USA
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Thanks for the pointer to the CE C SDK.
Even though I asked about C, the spasm-ng assembler can do eZ80 code. Also, the Y80e core is available that is supposed to be more efficient than the T80 or a-z80; see https://github.com/freecores/y80e
But this is a bit off topic for this thread.
For the Z280, there are, as far as I know, the following toolchains:
- John Coffman has done some work on the assembler for sdcc, but I don't know where that work stands
- Anders Ostlund has done some work on an assembler for sdcc.
- The UZI280 libraries for HiTech C coupled with the freeware version, on either the CPU280's CP/M 3 or within UZI280.
- The PRE280 preassembler distributed with the CPU280 code. Source for this is lost, even by its author. Also usable under CP/M 3 (or the zxcc CP/M emulation subsystem from Windows or Linux).
- Hector Peraza's Z280 assembler.
I feel like I'm forgetting some, and I apologize if I have.
If a Z280 generator and libs could be written for either the z88dk tool chain or the sdcc toolchain, it would be good.
For other compilers, if it can run on a PDP11 it should be able to run on Z280, if you want native development. I would defer to Alan's expertise on which modern cross compiler chain would be more desirable.
For CP/M the BDS C compiler is completely open, and maybe this could be ported and used for Z280 code generation.
--
Bughlt: Sckmud
Shut her down Scotty, she's sucking mud again!
[Updated on: Sat, 17 February 2018 06:46] Report message to a moderator
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Re: TinyZZ, a Z280 SBC [message #4379 is a reply to message #4378] |
Thu, 22 February 2018 06:32   |
plasmo
Messages: 916 Registered: March 2017 Location: New Mexico, USA
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Distraction, distraction and another distraction. This is why this is a hobby: distraction is far more interesting than the goal (which is CPM3 upgrade, I have to remind myself every morning)
#1: Martin Eberhard has released Xmodem 2.7 on comp.os.cpm several months ago. I finally was able to try it on TinyZ280. I can receive file from PC just fine, but at 57600 serial baud rate I think my PC is choking on the incoming serial stream. My terminal software is Tera Term. Even so, I'm happy to have it. This is a critical capability I needed so I can edit/assemble/test on my PC and then download the file to TinyZ280 to run.
#2: Another Martin on comp.os.cpm found an old copy of vi from a book by W. Miller A Software Tools Sampler. He and Udo Munk corroborated and came up with a working vi! I downloaded and ran it on TinyZ280 and it works. The cursor controls are the old 'HJKL' keys. Someone probably will fix that later on. Very cool, I might even entertain writing small program in the native CP/M environment.
#3: Received 10 Z280 from UTSource this week. With that I have enough parts and test software to do margin tests of the design. I tested 13 16-meg SIMM DRAM modules with the 10pcs Z280 over voltage range from 4.8V to 5.3V running RAM diagnostics and CP/M PIP with verify. All 10 Z280 passed, but 3 out of the 13 SIMM modules failed at high voltage. That were curious because parts run faster at higher voltage, but faster parts swinging over greater voltage range also generate more ground noises and ground bounce is always a concern with 2-layer pc board. I added a couple more ground wires to the board and all three DRAM modules passed the tests.
This reminds me of the curious problem with CPU280 where faster PAL part caused problem that was fixed with a slower part. Perhaps Z280 is more susceptible to ground noise. I examined the board layout of the CPU280. It is 2-layer board, but the board was beautifully designed with robust grid-like ground network. I did noticed there is only one 10uF capacitor. DRAM is a real noise maker, so I'd suggest if anyone experienced memory problem with CPU280 to add a couple more 10uF capacitors close to the DRAM array.
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rhkoolstar, thanks for the program, I'll modify it for my RAM disk which has 512 directory entries and I used Z280's MMU which has 4K size page. Right now my hardware boots to a monitor where I can erase the RAM disk directory before boot to CP/M. Eventually I'll boot straight to CP/M, so rdinit is a good utility to have.
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Re: TinyZZ, a Z280 SBC [message #4406 is a reply to message #4405] |
Fri, 02 March 2018 08:43   |
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lowen
Messages: 226 Registered: August 2016 Location: Western NC USA
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Senior Member |
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Quote:I'm beginning to question Z280's reputation for being buggy.
I'm beginning to wonder myself. I have relied on and deferred to Tilmann Reh's experiences along with information from several users of the Z280, but that information is almost all pre-92, and I've seen datecodes now as late as 97. So I guess it's possible that some bugs actually were fixed, but since the bugs weren't documented neither were the fixes. I've not disassembled the Specialix firmware for their SI/XIO ISA card from the Linux kernel drivers; that might be interesting to see if any of the workarounds were used.
I know I'm questioning the quantity manufactured, or the wisdom that the Z280 never really was commercially successful. I mean, there are ten years' worth of production (according to datecodes) out there, and UTSource is claiming 30,000+ stock on chips. And every order I've placed has been filled, quickly, so they apparently have stock of some size to do that.
The CPU280 does some pretty significant wait state generation for I/O, but that's primarily because of the ECB interfacing.
I'm loving where you're taking this beast, Plasmo!
--
Bughlt: Sckmud
Shut her down Scotty, she's sucking mud again!
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Re: TinyZZ, a Z280 SBC [message #4410 is a reply to message #4406] |
Sun, 04 March 2018 08:09   |
plasmo
Messages: 916 Registered: March 2017 Location: New Mexico, USA
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lowen wrote on Fri, 02 March 2018 09:43Quote:I'm beginning to question Z280's reputation for being buggy.
I'm beginning to wonder myself. I have relied on and deferred to Tilmann Reh's experiences along with information from several users of the Z280, but that information is almost all pre-92, and I've seen datecodes now as late as 97. So I guess it's possible that some bugs actually were fixed, but since the bugs weren't documented neither were the fixes. I've not disassembled the Specialix firmware for their SI/XIO ISA card from the Linux kernel drivers; that might be interesting to see if any of the workarounds were used.
The 15pcs of Z280 I have are from 1992 to 1997 so that's consistent with what you have. The earlier Z280 may have bugs, but Zilog had a number of years to correct that and it is hard to imagine they'll leave the more significant bugs as they were during all 10 years of production.
I re-read Tilmann Reh's description of Z280 bugs (section 10 of CPU280 Software Manual):
* OUTJMP bug is associated with I/O-write with wait state. This applies to both CPU access as well as DMA access. I can confirm that without wait state in I/O-write, the CPU access is not subject to the OUTJMP bug. I have not tried I/O write with DMA so far.
* DIVUW gives wrong results.
* DMA may not release the bus after I/O write for up to 20uS. There is a software fix named "Stefan Nitschke Chaos" for that.
* CPU may have invalid carry flag when instruction is sandwiched between two EX AF,AF' instructions. That error is also influenced by whether cache is enabled or not.
I'm ready to turn on DMA for CF and RAM disk data transfer so I will soon find out whether OUTJMP bug applies to DMA transfer of zero-wait I/O and whether DMA hangs on to the bus for up to 20uS. Any one know what is "Stefan Nitschke Chaos"? I imagine that code is implemented in UZI280?
I can understand the race of flag register updating its condition while it is been swapped out. Running with cache enabled will aggrevate that race condition even more. So turning off cache is a simple & quick test when encountering strange results.
I have not look into CPU280's BIOS nor UZI280. I imagine the specific bug fixes were documented in the codes. It may be interesting to remove these bug fixes and see if CPU280 with later date code Z280 still work or not. It is also interesting to port UZI280 and CPU280's BIOS to TinyZ280 with or without the bug fixes and see what happened.
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Re: TinyZZ, a Z280 SBC [message #4422 is a reply to message #4414] |
Tue, 06 March 2018 19:13   |
plasmo
Messages: 916 Registered: March 2017 Location: New Mexico, USA
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This was what Tilmann Reh said about DIVUW bug:
The DIVUW gives wrong results in certain cases. Such a case is the MSB (bit15) of the divisor being set.
So I tried divide 0x20000000 by 0x8888 and get 0x3c00 quotient and 0x2000 remainder. Try 0x20000000 divide by 0x4888 get 0x70F1 quotient and 0x37F8 remainder. These are the correct answers according to my calculator. I tried three different addressing modes:
divuw[dehl],(addr), divuw[dehl],bc, and divuw[dehl],ix, all give the same answers.
Fritz had got Tilmann's board and has picture of it here: https://www.retrobrewcomputers.org/forum/index.php?t=msg& ;th=93&goto=4162&#msg_4162
The date code of Tilmann's Z280 is 8735. The date code of my Z280 that I just did the divuw tests is 9332. So perhaps the divuw bug is fixed since mid 1987.
I remember someone had said somewhere that 'step J' has the bugs fixed. I don't know how to identify the step. The parts I have all have a 2-letter designation on the same line as the date code, but all 15 Z280 have different 2-letter designations.
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Re: TinyZZ, a Z280 SBC [message #4428 is a reply to message #4427] |
Wed, 07 March 2018 08:13   |
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lowen
Messages: 226 Registered: August 2016 Location: Western NC USA
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Senior Member |
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One of the best sources of information on Z80 is Rodnay Zaks' book. Rodnay has given permission for a PDF to be posted online, and you can grab it from the links at the end of this page. For that matter, the whole 'www.z80.info' site is a gold mine, but it needs more Z280, Z380, and eZ80 information. (Z380 and eZ80 are current production, but since both are only available in surface-mount packages, they haven't been as popular with hobbyists)
--
Bughlt: Sckmud
Shut her down Scotty, she's sucking mud again!
[Updated on: Wed, 07 March 2018 08:14] Report message to a moderator
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Re: TinyZZ, a Z280 SBC [message #4446 is a reply to message #4422] |
Thu, 15 March 2018 22:47   |
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fritzeflink
Messages: 80 Registered: January 2017 Location: germany
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plasmo wrote on Wed, 07 March 2018 04:13This was what Tilmann Reh said about DIVUW bug:
The DIVUW gives wrong results in certain cases. Such a case is the MSB (bit15) of the divisor being set.
So I tried divide 0x20000000 by 0x8888 and get 0x3c00 quotient and 0x2000 remainder. Try 0x20000000 divide by 0x4888 get 0x70F1 quotient and 0x37F8 remainder. These are the correct answers according to my calculator. I tried three different addressing modes:
divuw[dehl],(addr), divuw[dehl],bc, and divuw[dehl],ix, all give the same answers.
Fritz had got Tilmann's board and has picture of it here: https://www.retrobrewcomputers.org/forum/index.php?t=msg& ;amp ;amp ;th=93&goto=4162&#msg_4162
The date code of Tilmann's Z280 is 8735. The date code of my Z280 that I just did the divuw tests is 9332. So perhaps the divuw bug is fixed since mid 1987.
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The buggy old Z280 is mine. Very interesting info from you reading just as I can't sleep.
The CPU280 with the old Z280 stop after the ram test. I hope I got help next month from a 'developer' as I'm only a mechanic.
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fritz
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[Updated on: Thu, 15 March 2018 22:48] Report message to a moderator
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Re: TinyZZ, a Z280 SBC [message #4448 is a reply to message #4410] |
Fri, 16 March 2018 03:12   |
hperaza
Messages: 68 Registered: March 2017
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[quote title=plasmo wrote on Sun, 04 March 2018 08:09]lowen wrote on Fri, 02 March 2018 09:43I'm ready to turn on DMA for CF and RAM disk data transfer so I will soon find out whether OUTJMP bug applies to DMA transfer of zero-wait I/O and whether DMA hangs on to the bus for up to 20uS. Any one know what is "Stefan Nitschke Chaos"?
It's a section of code inside the DskIO routine, diskio.280 file. Basically, the DMA bug causes the data transfer from the FDC controller to fail with a DMA underrun error. When that happens, the code "fixes" the bug by writing four null words to four consecutive I/O addresses starting at FFxxE8. The mystery being that those addresses do not correspond to anything (documented, at least), that the fix has to be applied only when the bug is triggered, and that it needs to be applied only once (at least according to the code logic). So a second FDC DMA underrun error is supposed to be a floppy or FDC fault. The fix is never applied for hard disk (GIDE) DMA transfers, since IDE data transfers are not time-critical and there is no easy way to tell if the DMA bug happened in that case.
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Re: TinyZZ, a Z280 SBC [message #4449 is a reply to message #4448] |
Fri, 16 March 2018 05:59   |
plasmo
Messages: 916 Registered: March 2017 Location: New Mexico, USA
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FFxxE8 is the refresh controller (section 9.3 of Preliminary technical manual). I don't know what the next three I/O address after FFxxE8 are. Writing zero to FFxxE8 will disable the refresh controller but that will cause my board to crash, but I have not find out why exactly. To turn off the refresh controller, I would clear bit 7 (enable bit), but write non-zero values to remaining 7 bits. Since I do use the refresh counter for the DRAM, it is enabled and programmed to 16uS refresh.
I begin to understand why the unexpected 20uS delay: The refresh counter keeps track of how many refresh cycles it missed when Z280 bus mastership is relinquished to alternate bus masters (such as DMA). When Z280 regained the bus mastership, the refresh counter will take over immediately and make up for the refresh cycles it missed. This could be quite a number of cycles so Z280 appears to stalled during that period. At reset the refresh counter defaults to a refresh every 32 CPU clocks (about 2.6uS) so if DMA takes away 200uS from CPU bus mastership, the refresh counter will take 20uS to make up for the missing refresh cycles. Turning off the refresh counter will stop it from taking over the Z280 bus, but only until next reset.
CPU280 have DRAM as well, so it must have a different way of refreshing the memory and not relying on the internal refresh counter.
[Updated on: Fri, 16 March 2018 06:04] Report message to a moderator
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Re: TinyZZ, a Z280 SBC [message #4450 is a reply to message #4447] |
Fri, 16 March 2018 06:22   |
plasmo
Messages: 916 Registered: March 2017 Location: New Mexico, USA
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hperaza wrote on Fri, 16 March 2018 03:40plasmo wrote on Tue, 30 January 2018 06:57I'm leaning toward porting CP/M because it may test the board more thoroughly and also let me try Hector Peraza (hperaza) Z280 assembler ( https://www.retrobrewcomputers.org/forum/index.php?t=msg& ;amp ;amp ;amp ;th=93&goto=3700&#msg_3700). Right now I'm hand assembling the few Z280 extended instructions I needed.
You can use the Z280 assembler on Unix/Linux with a tool like John Elliott's ZXCC. There is a Windows port available somewhere as well.
The advantage of ZXCC over other CP/M emulators like e.g. z80pack is that with ZXCC you can run any CP/M utility directly from the command line (or from a Makefile), and access files on the host filesystem without having to put everything first in a virtual disk. ZXCC is used, for example, to cross-build CP/M 3 for the CPU280; that's the tool I used as well to develop and test the assembler.
BTW, I love your TinyZ280 board; I just added it to my TODO list . The CPLD is a clever addition that makes it more versatile while keeping the component count down.
Thank you for the pointer to ZXCC. The wonderful thing about the Z80 community is there are so many resources for every development environment and the bad thing about the Z80 community is there are so many resources for every development environment. Without someone points the way, a newbie like me can get bogged down trying every different tools.
CPLD is the heart of the design. I've learned my lesson from Tiny68K where CPLD is completely used up without any spare pins and logic. Booting from CF is a simpler design that gives me a dozen spare pins and 25% spare logic thus more room to play!
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Re: TinyZZ, a Z280 SBC [message #4452 is a reply to message #4449] |
Sat, 17 March 2018 05:53   |
hperaza
Messages: 68 Registered: March 2017
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plasmo wrote on Fri, 16 March 2018 05:59FFxxE8 is the refresh controller (section 9.3 of Preliminary technical manual). I don't know what the next three I/O address after FFxxE8 are. Writing zero to FFxxE8 will disable the refresh controller but that will cause my board to crash, but I have not find out why exactly. To turn off the refresh controller, I would clear bit 7 (enable bit), but write non-zero values to remaining 7 bits. Since I do use the refresh counter for the DRAM, it is enabled and programmed to 16uS refresh.
Indeed, just consulted the manual and is there. I was quoting the source code comments, and it looks like either the register was not documented at the time, or Stefan Nitschke did not have access to the full documentation. Interestingly, there is an entry for the register in the z280equ.mac file.
Your explanation of the DMA delay makes full sense, and the 'bug' starts looking now more like a design 'feature' than a real bug. And since the workaround was found "by accident", the additional writes to the FFxxE9..EB addresses are very likely superfluous.
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Re: TinyZZ, a Z280 SBC [message #4453 is a reply to message #4428] |
Sat, 17 March 2018 06:31   |
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fritzeflink
Messages: 80 Registered: January 2017 Location: germany
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lowen wrote on Wed, 07 March 2018 17:13One of the best sources of information on Z80 is Rodnay Zaks' book. Rodnay has given permission for a PDF to be posted online, and you can grab it from the links at the end of this page. For that matter, the whole 'www.z80.info' site is a gold mine, but it needs more Z280, Z380, and eZ80 information. (Z380 and eZ80 are current production, but since both are only available in surface-mount packages, they haven't been as popular with hobbyists)
For german people you can get Zaks_Programmierung_des_Z80.pdf at
http://oldcomputers.dyndns.org/public/pub/manuals/ and scroll down for download.
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fritz
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Re: TinyZZ, a Z280 SBC [message #4454 is a reply to message #4410] |
Sat, 17 March 2018 07:00   |
hperaza
Messages: 68 Registered: March 2017
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plasmo wrote on Sun, 04 March 2018 08:09* CPU may have invalid carry flag when instruction is sandwiched between two EX AF,AF' instructions. That error is also influenced by whether cache is enabled or not.
You can find the original bug report here.
My CPU (date code 9528) has the bug, and I can reproduce it consistently with any variations of the same sequence, e.g.:
scf
ex af,af'
xor a
ex af,af'
It is not that the carry bit disappears, but that the second ex af,af' instruction copies the flags register instead of swapping it (the accumulators are swapped as expected). For example, after the following sequence:
xor a ;clear sign and carry
ex af,af'
or 0FFh ;set sign flag
ex af,af'
both F and F' are identical: Carry and Zero bits clear, Sign and Even parity bits set. The pattern seems to be: one single arithmetic or logical instruction that uses the ALU sandwiched between two ex af,af' instructions. Thus, if the instruction is a load operation, or a rotate, nop, scf, etc. the bug will not be triggered. Neither it will if the "sandwich" consists of two or more instructions. Those are my observations so far.
How can it depend on the specific memory location (for me it happens when the starting address of the sequence is e.g. 100h, 1000h, 2000h, 8000h, etc. but not if it is e.g. 9E75h), or if cache is enabled/disabled is unclear to me. An easy fix is to add at least a nop after the arithmetic instruction, easy to do when developing new software, but difficult to fix for existing applications.
[Updated on: Sat, 17 March 2018 07:04] Report message to a moderator
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