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Re: Jackalope Progress [message #5947 is a reply to message #5946] Tue, 12 February 2019 04:02 Go to previous messageGo to next message
stevemoody is currently offline  stevemoody
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I've been looking at the KISS-68030 as well.

My plan is to have a single board computer which is why I was looking the the jackalope as a base but I'm planning to have a couple of expansion slots on there for adding extra peripherals as well. For the expansion ports I'm considering something alone the lines of the ECB bus so using the KISS-68030 may be a good starting point.

I may still be interested in using the DP8422V for the DRAM as considering using it with 4 banks to get 64M of RAM although that could be overkill.
Re: Jackalope Progress [message #5948 is a reply to message #5947] Tue, 12 February 2019 07:52 Go to previous messageGo to next message
jcoffman is currently offline  jcoffman
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The KISS-68030 DRAM controller will run 60ns DIMMs, 33mhz CPU, at 1 wait state. It supports 256Mb of memory. With slower CPU's, it may be run at 0 w.s. Will's Linux port to this card requires a minimum of 32Mb.

The KISS board does not use damping resistors on the DRAM data, address, or control lines. Hence, those traces need to be very short -- and they are on a 100mm x 160mm EuroCard.

The biggest need on the RetroBrew bus is a good Ethernet card -- especially for any Linux machine.

--John


Re: Jackalope Progress [message #5970 is a reply to message #5948] Tue, 19 February 2019 01:54 Go to previous messageGo to next message
stevemoody is currently offline  stevemoody
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Thanks John,

I've been looking at the DRAM controller for the KISS and will probably end up going with that. Part of the reason I liked the idea of using the DP8422 was to avoid having to deal with the DRAM refresh logic which give me a headache but it looks like the logic seems reliable at quite a range of speeds.

Will start a new thread when I make a start on the design.
Re: Jackalope Progress [message #5971 is a reply to message #5970] Tue, 19 February 2019 04:55 Go to previous messageGo to next message
plasmo is currently offline  plasmo
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The DRAM controller is simple enough that you can put them in a modest CPLD and have enough logic remaining to support 68030's decoding needs. I did that with Tiny030.

Over last 6 months I've sent out 3 Tiny030 pc boards even though it requires significant hand wiring. This round of discussion have encourage me to look at 68030 again. I've learned a couple things since and perhaps I can incorporate them in this new effort.
Bill
Re: Jackalope Progress [message #5976 is a reply to message #5971] Wed, 20 February 2019 06:57 Go to previous messageGo to next message
mikemac is currently offline  mikemac
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I actually pulled my Jackalope PCB out a couple of weeks ago to look at. And then I put it back. Too many obsolete parts for my preference, including the DRAM controller.

Speaking of obsolete parts, I see the Altera 7000S series is now marked "Obsolete" on Digikey. That isn't a show stopper in itself but the fact they have none in stock is bad news to me. Sad

How about a 68040V with a Max10 design? Nice 3.3 volts all around! Smile The Max10 also has on-board flash for a boot ROM! It'll supposedly do DDR2/DDR3 but SDRAM is good enough for me.

Instead of mucky with Jackalope, I'm back playing with a 3 chip idea: MC68SEC000, Max10, and 8Mx16 SDRAM. Hopefully I can get it placed and routed and sent off to the fab house this weekend. I just wish you could still get FPGAs in those 200-250 pin QFPs like the old Cyclone 2s.



Mike
Re: Jackalope Progress [message #5977 is a reply to message #5976] Wed, 20 February 2019 08:33 Go to previous messageGo to next message
plasmo is currently offline  plasmo
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Mike,
I buy Altera 7000S from UTSource and am generally happy with their parts. Altera 7128 should be pin compatible with Atmel ATF1508 which is still in stock. There is a conversion program from Altera' POF programming file to Atmel programming file. I have not check it out, however.

Of course 68040 (5V) is also obsolete. 68040V (3.3V) is even more difficult to find. I'm not keen on 68040 because heat management is a big issue.

I dug out my Tiny030 pc board yesterday and had a couple ideas about building and testing it in stage.
1. Start with programming CPLD and blink a few LED, to
2. minimum functioning 68030 with 3 chips, to
3. a basic 68030 with 5 chips, to
4. full-up 68030 with 16-meg DRAM, and eventually to
5. CP/M-68K ready 68030 computer.

Done stage 1, fiddling around with stage 2 right now. Stage 3 & 4 were done 2 years ago, I need to revisit & refresh my memory. Not sure how to do stage 5 with the existing board.
Re: Jackalope Progress [message #5981 is a reply to message #5977] Wed, 20 February 2019 16:40 Go to previous messageGo to next message
mikemac is currently offline  mikemac
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Ebay claims there are 68040V's in China for only $15! Yeah right!

Bill, are you thinking of reimplementing the KISS030 design but using a CPLD instead of the discrete TTL logic? A SBC or with an expansion bus? Or should I think of it as more of a Tiny68K with an up scaled 68030 CPU? A 68030 seems like it'd be extreme overkill for CPM.

Steve, what kind of system are you thinking about? SBC? Expansion bus? Peripherals? Memory configuration? OS? SW?

Mike



Mike
Re: Jackalope Progress [message #5982 is a reply to message #5981] Wed, 20 February 2019 18:15 Go to previous messageGo to next message
plasmo is currently offline  plasmo
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It is Tiny68K but with 68030 instead. CP/M68K is the easy OS to implement. I would like UNIX, but it is beyond my current skill level. Tiny68K actually does have an expansion connector in form of 2nd SIMM72 connector. I haven't done a thing with it, but maybe Tiny030 could use the expansion capability.

I'm hoping for Field of Dreams for Tiny030-- 'build it and they will come'. Cool
Bill
Re: Jackalope Progress [message #5983 is a reply to message #5981] Thu, 21 February 2019 08:13 Go to previous messageGo to next message
stevemoody is currently offline  stevemoody
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mikemac wrote on Wed, 20 February 2019 16:40

Steve, what kind of system are you thinking about? SBC? Expansion bus? Peripherals? Memory configuration? OS? SW?
What I was planning on is a SBC with a few peripherals probably serial, ethernet and an IDE interface. I'm also planning on a couple of expansion ports that will allow any other peripherals to be added. Memory will probably be an EEPROM, small about of SRAM and then DRAM for the main memory.

Not sure about OS yet but getting Linux up and running will probably be a goal. Still very early in the planning stage at the moment so more details will come as I have a better idea of what I want.

plasmo wrote on Tue, 19 February 2019 04:55
The DRAM controller is simple enough that you can put them in a modest CPLD and have enough logic remaining to support 68030's decoding needs. I did that with Tiny030.
I was thinking of using a CPLD instead of GALs anyway so will have a look at this later this evening.

Steve

Re: Jackalope Progress [message #5984 is a reply to message #5983] Thu, 21 February 2019 11:54 Go to previous messageGo to next message
yoda is currently offline  yoda
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I am interested in similar thing - I have the Jackalope board a lot is functional but too many peripherals and not enough dram and the controller is hard to use. I would like to see a CPLD implementation of DRAM like what BILL has done but as a set of Verilog equations instead of Altera circuit diagram - would be more useful and a little easier to understand. I moved over the summer from Texas to Iowa and pretty much have my electronics workshop back up and functioning. I would like to see an initial board with eeprom, sram, dram, dual serial ports (ttl level), programmable timer for interrupts, and iDE interface. The Jackalope board pretty much had that but with a lot of extra stuff. If the video, keyboard controller, and ethernet could be stripped initially or a more modern ethernet controller substituted it would be a reasonable place to start. Having a reliable 256 - 512 M Dram on board using a Altera CPLD would be desirable. I have tons of them around. Maybe I will throw a circuit together. I would like to do a 68040 someday but bus resizing is another issue to tackle that the 030 does not have
Re: Jackalope Progress [message #5985 is a reply to message #5984] Thu, 21 February 2019 13:50 Go to previous messageGo to next message
mikemac is currently offline  mikemac
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That's the short coming of a SBC: it's one size fits all. And we all have such diverse desires.

For me, it's SATA or an SD card. IDE drives went the way of the Dodo bird. I think I have one or two around but I wouldn't use them for anything. For me, 64-128MB of DRAM would be fine. Should be enough for Linux. I'd actually prefer it to be TSOP-54's on the board. Unused chip sites for more RAM is OK too. I don't need SRAM. MUST have 32 bit wide memory path. No running a 32 bit processor in 8 bit mode! And only enough boot ROM for a minimal boot loader to load from SD card or SATA. And since I want Ethernet and graphics, some kind of expansion bus so I can add those thing I want and no one else is interested in. Smile

But that's why I've been asking if Bill and Steve are looking at a SBC. I think the better approach is a bus based system. Or at least someting with expansion slots ala m-ATX or m-ITX. Maybe something like an expanded ECB. I've looked at VME, NuBus, ISA, PCI, Zorro II & III, ... Never found the MultiBus (II) info, which is surprising. None of them are a perfect match for my dream. So once I get my next 68SEC000 paper design done, I'm going to make up my own bus.

I'll have to go back and look at the 040 data sheet again. I didn't think the data bus requirements were that onerous.

Mike



Mike
Re: Jackalope Progress [message #5986 is a reply to message #2502] Thu, 21 February 2019 13:55 Go to previous messageGo to next message
tobster is currently offline  tobster
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I noticed the recent activity in this thread and thought I would give an update on my take on a 68030-based SBC.

Several moons ago, I posted this:

https://www.retrobrewcomputers.org/forum/index.php?t=msg& ;goto=791

Last year I found the time to make a second version, incorporating the mess into one single board. The DRAM has been extended to 64 MB (4 x 16 MB 30-pin SIMM), and an IDE port has been added.

It runs Debian m68k just like KISS-68030 (I borrowed the disk image from Will's Linux port as a starting point), with a custom lightweight startup script based on Busybox init. I have just upgraded to kernel version 4.9.156

So far I have built two of these boards, one of them has been built into an old Mini-ITX enclosure with a 2.5" harddisk, an ENC28J60 ethernet module and an SD card adapter.

If anyone is interested, I can create a builderpage on the wiki with updated KiCad design files, Linux kernel patch, Altera projects etc.

/Tobias

Re: Jackalope Progress [message #5987 is a reply to message #5986] Thu, 21 February 2019 14:32 Go to previous messageGo to next message
mikemac is currently offline  mikemac
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Neat! Your old T030.pdf schematics are one of the ones I look at whenever I start dreaming about such a board.

Please do create a builder's page and share as much as you'd like. I'm definitely interested in snooping! Smile

Well done!

Mike



Mike
Re: Jackalope Progress [message #5988 is a reply to message #5985] Thu, 21 February 2019 18:03 Go to previous messageGo to next message
yoda is currently offline  yoda
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SRAM is almost a must for bring up. In regards to IDE, Complact Flash cards work very nice and are easier to do software for than bit banging SD cards. I think 256 meg was a minimum to get a Linux Kernel to boot on it on the KISS system.
Re: Jackalope Progress [message #5989 is a reply to message #5986] Thu, 21 February 2019 18:27 Go to previous messageGo to next message
yoda is currently offline  yoda
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Tobias

I like your design - is there a way to use larger dimms and you did use equations if I recall? I think it might be a good launch point. I have been using the larger Altera CPLDs on breakout boards - may be able to condense your 2 to one - I would have to think on it a bit.

Dave
Re: Jackalope Progress [message #5990 is a reply to message #5988] Thu, 21 February 2019 18:55 Go to previous messageGo to next message
mikemac is currently offline  mikemac
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Although having SRAM makes bring up easier, it does cost significantly more than SDRAM. 16MB: SDRAM - $2.50, SRAM - $50 @ Digikey. And that's for 55ns SRAM. Fast SRAM gets pricey really quickly.

As I'm sure everyone is aware of, bring up can be done with ROM and the CPU registers with a bit of care. On MIPS processors, we often brought boards up without the RAM. But the MIPS had a data cache so you could pretend you had RAM as long as you didn't use too much of it and force a cache flush. If that happened, bad things happen.

And once bring up is done, the SRAM just gets gets in the way and mucks up the address space.

I didn't know the KISS030 board would go up to 256MB. All of the sizes on the board's page are listed in Mb. But if you need 256MB for Linux, I think something is seriously wrong. I was running a 4.20 kernel with Busybox in 32MB of SDRAM on a ARM Cortex-m4 last week. I know ARM vs 68K isn't exactly apples to apples but a factor of 8 or more seems big.



Mike
Re: Jackalope Progress [message #5991 is a reply to message #5990] Thu, 21 February 2019 20:01 Go to previous messageGo to next message
yoda is currently offline  yoda
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Well a 512k sram is more than sufficient is about 8 bucks - worth the headache of reprogramming ROMs and with a simple monitor it is nice to use zmodem to download new version into SRAM which is easy to get working before dram. Kiss had a 32k byte sram on if of similar cost for the same reason. Don't underestimate bring up and having a reliable serial loader - I could debug iteratively and burn eeprom once a day with updates.
Re: Jackalope Progress [message #5993 is a reply to message #5988] Fri, 22 February 2019 07:49 Go to previous messageGo to next message
jcoffman is currently offline  jcoffman
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Will's Linux port to the KISS-68030 ran in 32Mb. With 72-pin DIMM's running $10 for 64Mb, it was not too painful to go to 2 x 128Mb strips for $40. [1-800-4memory on eBay]

--John


Re: Jackalope Progress [message #5994 is a reply to message #5991] Fri, 22 February 2019 07:52 Go to previous messageGo to next message
jcoffman is currently offline  jcoffman
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The 32K SRAM on the KISS-68030 was sufficient for DRAM testing. Once the DRAM controller got a clean bill of health, in actual OS operation, SRAM is not used.

--John
Re: Jackalope Progress [message #5996 is a reply to message #2502] Fri, 22 February 2019 09:16 Go to previous messageGo to next message
mikemac is currently offline  mikemac
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My reluctance to a small SRAM was from dealing with full data bus width systems where you'd need 4 SRAM chips plus 4 FLASH chips just to fit the data bus requirements. But with the 68030's ability to dynamically resize the data bus size, you only need a single SRAM and a single FLASH fro boot/bring up and you can stiil run the DRAM at the full 32 bit width. If I understand the bus resizing correctly.

In systems that only support one, static data bus size, then Bill's trick of having the CPLD load RAM from a serial ROM before releasing the processor from reset is the way to go. But that isn't required for a 68030 but would be for a 68040. Unless you added a 68150 to the 68040 but that adds more complications.

Bill, thanks for reminding me of UTsource. I hadn't looked there in a couple of years. It funny though that if you search for 7128s, it finds 9 items, 3 of which are the EPM7128s. But if you search for epm7128s, it finds 168 items! Guess you have to play with what you search for to get the best results.



Mike
Re: Jackalope Progress [message #5997 is a reply to message #5993] Fri, 22 February 2019 09:30 Go to previous messageGo to next message
mikemac is currently offline  mikemac
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jcoffman wrote on Fri, 22 February 2019 08:49
Will's Linux port to the KISS-68030 ran in 32Mb. With 72-pin DIMM's running $10 for 64Mb, it was not too painful to go to 2 x 128Mb strips for $40. [1-800-4memory on eBay]

--John


And brand new 64MB SDRAM chips are $13 at Digikey. Going new means you don't have the cost of the connectors nor the worry about whether the used DIMMs still work. And they take up less vertical space. The DIMMs do have the advantage of being more flexible to resize after your board is built.

Trade offs. Trade offs.



Mike
Re: Jackalope Progress [message #5998 is a reply to message #5996] Fri, 22 February 2019 09:41 Go to previous messageGo to next message
yoda is currently offline  yoda
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I did pickup some 68150s a while back on eBay in anticipation of doing an 040 implementation - but the more I look - it is probably easier to just do the mapping in a CPLD but I want to get a stable DRAM system before I start on that board. I have plenty of 030s and 68xxx peripheral chips so I think something like Bill has done as a start. I have stable development environment that I can do all coding in C and zmodem support in my monitor so with small sram I can do a lot of easy debugging of DRAM and other peripherals. If I get a stable reliable 030 design then I feel more comfortable doing an 040 design.
Re: Jackalope Progress [message #6000 is a reply to message #5996] Fri, 22 February 2019 10:12 Go to previous messageGo to next message
plasmo is currently offline  plasmo
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mikemac wrote on Fri, 22 February 2019 10:16
My reluctance to a small SRAM was from dealing with full data bus width systems where you'd need 4 SRAM chips plus 4 FLASH chips just to fit the data bus requirements. But with the 68030's ability to dynamically resize the data bus size, you only need a single SRAM and a single FLASH fro boot/bring up and you can stiil run the DRAM at the full 32 bit width. If I understand the bus resizing correctly.

In systems that only support one, static data bus size, then Bill's trick of having the CPLD load RAM from a serial ROM before releasing the processor from reset is the way to go. But that isn't required for a 68030 but would be for a 68040. Unless you added a 68150 to the 68040 but that adds more complications.

Bill, thanks for reminding me of UTsource. I hadn't looked there in a couple of years. It funny though that if you search for 7128s, it finds 9 items, 3 of which are the EPM7128s. But if you search for epm7128s, it finds 168 items! Guess you have to play with what you search for to get the best results.
68030 has the dynamic bus sizing capability so byte-wide, word-wide, long-word-wide memory can coexist in a system. The Tiny030 has a 8-bit wide RAM to help me bring up the board the first time. I'm thinking of designing it out in next revision, but for hobbyists new to 68030, it is very instructive to build and test the board in baby steps. A simple 3-chip ROM-less 68030 computer is possible with RAM/CPU/CPLD using the serial bootstrap method. I'm writing up a series of projects on Hackaday on how to build up a 68030 computer in 5 stages. https://hackaday.io/project/164041-building-a-68030-computer -in-5-stages
The simple 3-chip 68030 configuration is stage 2. I may retain the 8-bit RAM simply because it is so useful for incremental builds&tests of hardware.

68040 has no dynamic bus capability. All memory need to be 32-bit wide, unless 68150 is used.
Bill

Re: Jackalope Progress [message #6003 is a reply to message #5986] Sat, 23 February 2019 08:50 Go to previous messageGo to next message
mikemac is currently offline  mikemac
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The more I look at this board, the more impressed I am at what you've done. If it had a bus expansion port of some kind, I'd be trying to get one. But I want to be able to play with my own ideas for additions so a bus expansion port is a must have for me. And that's just me. Its your board so you get to do what you want!

I've never heard of the TI tp3465v before. Sure looks like "Microwire" is TI's name for SPI. That's a nice solution for that interface! I'll have to add that to my bag of tricks.

It looks like you're doing PIO mode to the IDE, with the two 74245s right next to the IDE cable. Correct?

Why the two 7128s? Did you just substitute out the SRAM in your original design with 4 SIMM slots and a dedicated 7128s? The option for more memory is always nice but 64MB is acceptable too.

You hard wired in the power supply. An ATX connector would have been nice. Once again, nice but not a complaint.

What's on P3? Extra 7128s pins?

Please do share your excellent design.



Mike
Re: Jackalope Progress [message #6006 is a reply to message #2502] Sat, 23 February 2019 14:33 Go to previous messageGo to next message
tobster is currently offline  tobster
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Thanks Mike!

I have created a builder page now:

https://www.retrobrewcomputers.org/doku.php?id=builderpages: tobster:start

At the bottom you will find the KiCad project files, schematics, Altera project files / VHDL source code, ROM BIOS source and Linux kernel patches.

I discovered the TP3465V when browsing for other retro projects and thought Hey, this is just what I need. Originally I was planning to create a SPI master in another CPLD. And yes, as I understand, microwire is just another name for SPI. The drawback with using the TP3465V is that is can be difficult to find and it's a bit expensive. But it works like a charm and I have made a simple Linux driver for it.

You are correct about the IDE PIO mode. This is just another case where the dynamic bus sizing on the 68030 comes in handy, the IDE interface is essentially just a simple 16 bit memory mapped port.

The choice of using two 7128s is simply because there are not enough io pins on one to do both glue logic and the DRAM controller. I could have used one of the larger MAX 7000 CPLDs, but I am still not comfortable soldering SMD components.

When I designed the board I didn't plan for mounting it in a Mini-ITX enclosure, I just later discovered that it almost fitted in an old one I had lying around. But yes, the board could have used something better that the simple screw connector for power.

P3 is actually an attempt of an expansion port. But it is mostly an afterthought, and more a place to hook up the logic analyzer if I need to debug the board. If I where to design another board I would put some more effort into a proper expansion port.

Dave, there should be nothing wrong with using larger memory modules with the DRAM controller. I kept the 30 pin SIMMs as I didn't want to change too many things at a time for the next iteration of the project. Plus I already had bought some 30 pin sockets. The glue logic for the first version was using the Altera Quartus schematic editor, but for the new version both the DRAM controller and glue logic is in VHDL which is much easier to follow and modify.


/Tobias



Re: Jackalope Progress [message #6015 is a reply to message #6006] Sun, 24 February 2019 09:56 Go to previous messageGo to next message
mikemac is currently offline  mikemac
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Thanks! I've grabbed a copy and have started studying it.

Just a minor nit: the "crystal" library can't be found when I open the schematic in KiCAD 4.0.6. It didn't offer to replace anything so it may not be being used.

I see you have two JTAG connectors, one for each CPLD. You're supposed to be able to daisy chain the TDO-TDIs in a loop so you only use on JTAG connector. I'm not sure how you keep track of which identical 7128s is which, other than by position in the chain. Anyway, that'd save you a small amount of board space, which appears to be pretty tight on your board.

Did you route this by hand or use "freeroute"?



Mike
Re: Jackalope Progress [message #6016 is a reply to message #2502] Sun, 24 February 2019 11:56 Go to previous messageGo to next message
tobster is currently offline  tobster
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I did contemplate using just one JTAG connector and daisy-chaining the two CPLDs, but as I was unsure if it would pose any problems with addressing the individual CPLDs from Quartus, I just took the simple approach and stuck two connectors on the board. I was planning on using proper connectors with the notch for keying instead of just the pin headers you see on the picture, but the space is too tight for them.

Apart from power traces to the DRAM sockets and the CPU, the whole board is routed by FreeRoute. I know a lot of people would say thats a big no-no, but I simply don't have the patience to do all the routing by hand. And I am really amazed by how effective FreeRoute is. I let it complete the routing, and then let it do its optimisation for a day or so, inspected the results, fixed one trace that was routed outside one of the corner holes, crossed my fingers and sent the design off for production.

There is one error on the board: The 74LS245's are flipped direction-wise, requiring two trace cuts and an extra inverted RW signal from the CPLD (see the picture of the bottom of the board).

/Tobias
Re: Jackalope Progress [message #6021 is a reply to message #6016] Mon, 25 February 2019 04:47 Go to previous messageGo to next message
plasmo is currently offline  plasmo
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I have a design with two Altera EPM7128 connected to one JTAG header. The position of the programming files determine which part get which programming files. The best way to find out is build a board with just the CPLDs, power it up and program them, then stick with the same file order.

I'm not sure what are the objections to autorouter. When the first reasonable autorouter became available in early 1980's, I immediately took advantage of it. I must've used a dozen different auto routers since and really don't have issues specifically related to autorouters. There certainly were a lot of mistakes made over the years, but they were mostly mine, can't blame them on the autorouters.
Bill
Re: Jackalope Progress [message #6022 is a reply to message #6021] Mon, 25 February 2019 05:04 Go to previous message
plasmo is currently offline  plasmo
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I wrote up the details of bringing up a minimal 68030 with 3 chips, CPU, RAM and CPLD. The CPLD serves the function of glue logic and a serial bootstrap loader that serially transfers 255 bytes of bootstrap code into RAM and then releases 68030 to run. Tiny030 pc board was not designed for multi-stages assembly so there are quite a bit of manual wiring. I want to revise the board design so it can be easily assembled & tested one baby step at a time. For hobbyists building the board first time, it is a desirable feature so assembly mistakes and faulty parts can be identified and corrected early on.
https://hackaday.io/project/164041-building-a-68030-computer -in-5-stages/log/159687-stage-2-a-minimal-68030-computer
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