|
|
|
|
|
Re: Jackalope Progress [message #5977 is a reply to message #5976] |
Wed, 20 February 2019 08:33 |
plasmo
Messages: 866 Registered: March 2017 Location: New Mexico, USA
|
Senior Member |
|
|
Mike,
I buy Altera 7000S from UTSource and am generally happy with their parts. Altera 7128 should be pin compatible with Atmel ATF1508 which is still in stock. There is a conversion program from Altera' POF programming file to Atmel programming file. I have not check it out, however.
Of course 68040 (5V) is also obsolete. 68040V (3.3V) is even more difficult to find. I'm not keen on 68040 because heat management is a big issue.
I dug out my Tiny030 pc board yesterday and had a couple ideas about building and testing it in stage.
1. Start with programming CPLD and blink a few LED, to
2. minimum functioning 68030 with 3 chips, to
3. a basic 68030 with 5 chips, to
4. full-up 68030 with 16-meg DRAM, and eventually to
5. CP/M-68K ready 68030 computer.
Done stage 1, fiddling around with stage 2 right now. Stage 3 & 4 were done 2 years ago, I need to revisit & refresh my memory. Not sure how to do stage 5 with the existing board.
|
|
|
Re: Jackalope Progress [message #5981 is a reply to message #5977] |
Wed, 20 February 2019 16:40 |
mikemac
Messages: 249 Registered: March 2017
|
Senior Member |
|
|
Ebay claims there are 68040V's in China for only $15! Yeah right!
Bill, are you thinking of reimplementing the KISS030 design but using a CPLD instead of the discrete TTL logic? A SBC or with an expansion bus? Or should I think of it as more of a Tiny68K with an up scaled 68030 CPU? A 68030 seems like it'd be extreme overkill for CPM.
Steve, what kind of system are you thinking about? SBC? Expansion bus? Peripherals? Memory configuration? OS? SW?
Mike
Mike
|
|
|
|
|
|
Re: Jackalope Progress [message #5985 is a reply to message #5984] |
Thu, 21 February 2019 13:50 |
mikemac
Messages: 249 Registered: March 2017
|
Senior Member |
|
|
That's the short coming of a SBC: it's one size fits all. And we all have such diverse desires.
For me, it's SATA or an SD card. IDE drives went the way of the Dodo bird. I think I have one or two around but I wouldn't use them for anything. For me, 64-128MB of DRAM would be fine. Should be enough for Linux. I'd actually prefer it to be TSOP-54's on the board. Unused chip sites for more RAM is OK too. I don't need SRAM. MUST have 32 bit wide memory path. No running a 32 bit processor in 8 bit mode! And only enough boot ROM for a minimal boot loader to load from SD card or SATA. And since I want Ethernet and graphics, some kind of expansion bus so I can add those thing I want and no one else is interested in.
But that's why I've been asking if Bill and Steve are looking at a SBC. I think the better approach is a bus based system. Or at least someting with expansion slots ala m-ATX or m-ITX. Maybe something like an expanded ECB. I've looked at VME, NuBus, ISA, PCI, Zorro II & III, ... Never found the MultiBus (II) info, which is surprising. None of them are a perfect match for my dream. So once I get my next 68SEC000 paper design done, I'm going to make up my own bus.
I'll have to go back and look at the 040 data sheet again. I didn't think the data bus requirements were that onerous.
Mike
Mike
|
|
|
Re: Jackalope Progress [message #5986 is a reply to message #2502] |
Thu, 21 February 2019 13:55 |
|
tobster
Messages: 11 Registered: June 2016 Location: Denmark
|
Junior Member |
|
|
I noticed the recent activity in this thread and thought I would give an update on my take on a 68030-based SBC.
Several moons ago, I posted this:
https://www.retrobrewcomputers.org/forum/index.php?t=msg& ;goto=791
Last year I found the time to make a second version, incorporating the mess into one single board. The DRAM has been extended to 64 MB (4 x 16 MB 30-pin SIMM), and an IDE port has been added.
It runs Debian m68k just like KISS-68030 (I borrowed the disk image from Will's Linux port as a starting point), with a custom lightweight startup script based on Busybox init. I have just upgraded to kernel version 4.9.156
So far I have built two of these boards, one of them has been built into an old Mini-ITX enclosure with a 2.5" harddisk, an ENC28J60 ethernet module and an SD card adapter.
If anyone is interested, I can create a builderpage on the wiki with updated KiCad design files, Linux kernel patch, Altera projects etc.
/Tobias
|
|
|
|
|
|
Re: Jackalope Progress [message #5990 is a reply to message #5988] |
Thu, 21 February 2019 18:55 |
mikemac
Messages: 249 Registered: March 2017
|
Senior Member |
|
|
Although having SRAM makes bring up easier, it does cost significantly more than SDRAM. 16MB: SDRAM - $2.50, SRAM - $50 @ Digikey. And that's for 55ns SRAM. Fast SRAM gets pricey really quickly.
As I'm sure everyone is aware of, bring up can be done with ROM and the CPU registers with a bit of care. On MIPS processors, we often brought boards up without the RAM. But the MIPS had a data cache so you could pretend you had RAM as long as you didn't use too much of it and force a cache flush. If that happened, bad things happen.
And once bring up is done, the SRAM just gets gets in the way and mucks up the address space.
I didn't know the KISS030 board would go up to 256MB. All of the sizes on the board's page are listed in Mb. But if you need 256MB for Linux, I think something is seriously wrong. I was running a 4.20 kernel with Busybox in 32MB of SDRAM on a ARM Cortex-m4 last week. I know ARM vs 68K isn't exactly apples to apples but a factor of 8 or more seems big.
Mike
|
|
|
|
|
|
Re: Jackalope Progress [message #5996 is a reply to message #2502] |
Fri, 22 February 2019 09:16 |
mikemac
Messages: 249 Registered: March 2017
|
Senior Member |
|
|
My reluctance to a small SRAM was from dealing with full data bus width systems where you'd need 4 SRAM chips plus 4 FLASH chips just to fit the data bus requirements. But with the 68030's ability to dynamically resize the data bus size, you only need a single SRAM and a single FLASH fro boot/bring up and you can stiil run the DRAM at the full 32 bit width. If I understand the bus resizing correctly.
In systems that only support one, static data bus size, then Bill's trick of having the CPLD load RAM from a serial ROM before releasing the processor from reset is the way to go. But that isn't required for a 68030 but would be for a 68040. Unless you added a 68150 to the 68040 but that adds more complications.
Bill, thanks for reminding me of UTsource. I hadn't looked there in a couple of years. It funny though that if you search for 7128s, it finds 9 items, 3 of which are the EPM7128s. But if you search for epm7128s, it finds 168 items! Guess you have to play with what you search for to get the best results.
Mike
|
|
|
Re: Jackalope Progress [message #5997 is a reply to message #5993] |
Fri, 22 February 2019 09:30 |
mikemac
Messages: 249 Registered: March 2017
|
Senior Member |
|
|
jcoffman wrote on Fri, 22 February 2019 08:49Will's Linux port to the KISS-68030 ran in 32Mb. With 72-pin DIMM's running $10 for 64Mb, it was not too painful to go to 2 x 128Mb strips for $40. [1-800-4memory on eBay]
--John
And brand new 64MB SDRAM chips are $13 at Digikey. Going new means you don't have the cost of the connectors nor the worry about whether the used DIMMs still work. And they take up less vertical space. The DIMMs do have the advantage of being more flexible to resize after your board is built.
Trade offs. Trade offs.
Mike
|
|
|
|
Re: Jackalope Progress [message #6000 is a reply to message #5996] |
Fri, 22 February 2019 10:12 |
plasmo
Messages: 866 Registered: March 2017 Location: New Mexico, USA
|
Senior Member |
|
|
mikemac wrote on Fri, 22 February 2019 10:16My reluctance to a small SRAM was from dealing with full data bus width systems where you'd need 4 SRAM chips plus 4 FLASH chips just to fit the data bus requirements. But with the 68030's ability to dynamically resize the data bus size, you only need a single SRAM and a single FLASH fro boot/bring up and you can stiil run the DRAM at the full 32 bit width. If I understand the bus resizing correctly.
In systems that only support one, static data bus size, then Bill's trick of having the CPLD load RAM from a serial ROM before releasing the processor from reset is the way to go. But that isn't required for a 68030 but would be for a 68040. Unless you added a 68150 to the 68040 but that adds more complications.
Bill, thanks for reminding me of UTsource. I hadn't looked there in a couple of years. It funny though that if you search for 7128s, it finds 9 items, 3 of which are the EPM7128s. But if you search for epm7128s, it finds 168 items! Guess you have to play with what you search for to get the best results.
68030 has the dynamic bus sizing capability so byte-wide, word-wide, long-word-wide memory can coexist in a system. The Tiny030 has a 8-bit wide RAM to help me bring up the board the first time. I'm thinking of designing it out in next revision, but for hobbyists new to 68030, it is very instructive to build and test the board in baby steps. A simple 3-chip ROM-less 68030 computer is possible with RAM/CPU/CPLD using the serial bootstrap method. I'm writing up a series of projects on Hackaday on how to build up a 68030 computer in 5 stages. https://hackaday.io/project/164041-building-a-68030-computer -in-5-stages
The simple 3-chip 68030 configuration is stage 2. I may retain the 8-bit RAM simply because it is so useful for incremental builds&tests of hardware.
68040 has no dynamic bus capability. All memory need to be 32-bit wide, unless 68150 is used.
Bill
|
|
|
Re: Jackalope Progress [message #6003 is a reply to message #5986] |
Sat, 23 February 2019 08:50 |
mikemac
Messages: 249 Registered: March 2017
|
Senior Member |
|
|
The more I look at this board, the more impressed I am at what you've done. If it had a bus expansion port of some kind, I'd be trying to get one. But I want to be able to play with my own ideas for additions so a bus expansion port is a must have for me. And that's just me. Its your board so you get to do what you want!
I've never heard of the TI tp3465v before. Sure looks like "Microwire" is TI's name for SPI. That's a nice solution for that interface! I'll have to add that to my bag of tricks.
It looks like you're doing PIO mode to the IDE, with the two 74245s right next to the IDE cable. Correct?
Why the two 7128s? Did you just substitute out the SRAM in your original design with 4 SIMM slots and a dedicated 7128s? The option for more memory is always nice but 64MB is acceptable too.
You hard wired in the power supply. An ATX connector would have been nice. Once again, nice but not a complaint.
What's on P3? Extra 7128s pins?
Please do share your excellent design.
Mike
|
|
|
Re: Jackalope Progress [message #6006 is a reply to message #2502] |
Sat, 23 February 2019 14:33 |
|
tobster
Messages: 11 Registered: June 2016 Location: Denmark
|
Junior Member |
|
|
Thanks Mike!
I have created a builder page now:
https://www.retrobrewcomputers.org/doku.php?id=builderpages: tobster:start
At the bottom you will find the KiCad project files, schematics, Altera project files / VHDL source code, ROM BIOS source and Linux kernel patches.
I discovered the TP3465V when browsing for other retro projects and thought Hey, this is just what I need. Originally I was planning to create a SPI master in another CPLD. And yes, as I understand, microwire is just another name for SPI. The drawback with using the TP3465V is that is can be difficult to find and it's a bit expensive. But it works like a charm and I have made a simple Linux driver for it.
You are correct about the IDE PIO mode. This is just another case where the dynamic bus sizing on the 68030 comes in handy, the IDE interface is essentially just a simple 16 bit memory mapped port.
The choice of using two 7128s is simply because there are not enough io pins on one to do both glue logic and the DRAM controller. I could have used one of the larger MAX 7000 CPLDs, but I am still not comfortable soldering SMD components.
When I designed the board I didn't plan for mounting it in a Mini-ITX enclosure, I just later discovered that it almost fitted in an old one I had lying around. But yes, the board could have used something better that the simple screw connector for power.
P3 is actually an attempt of an expansion port. But it is mostly an afterthought, and more a place to hook up the logic analyzer if I need to debug the board. If I where to design another board I would put some more effort into a proper expansion port.
Dave, there should be nothing wrong with using larger memory modules with the DRAM controller. I kept the 30 pin SIMMs as I didn't want to change too many things at a time for the next iteration of the project. Plus I already had bought some 30 pin sockets. The glue logic for the first version was using the Altera Quartus schematic editor, but for the new version both the DRAM controller and glue logic is in VHDL which is much easier to follow and modify.
/Tobias
|
|
|
Re: Jackalope Progress [message #6015 is a reply to message #6006] |
Sun, 24 February 2019 09:56 |
mikemac
Messages: 249 Registered: March 2017
|
Senior Member |
|
|
Thanks! I've grabbed a copy and have started studying it.
Just a minor nit: the "crystal" library can't be found when I open the schematic in KiCAD 4.0.6. It didn't offer to replace anything so it may not be being used.
I see you have two JTAG connectors, one for each CPLD. You're supposed to be able to daisy chain the TDO-TDIs in a loop so you only use on JTAG connector. I'm not sure how you keep track of which identical 7128s is which, other than by position in the chain. Anyway, that'd save you a small amount of board space, which appears to be pretty tight on your board.
Did you route this by hand or use "freeroute"?
Mike
|
|
|
Re: Jackalope Progress [message #6016 is a reply to message #2502] |
Sun, 24 February 2019 11:56 |
|
tobster
Messages: 11 Registered: June 2016 Location: Denmark
|
Junior Member |
|
|
I did contemplate using just one JTAG connector and daisy-chaining the two CPLDs, but as I was unsure if it would pose any problems with addressing the individual CPLDs from Quartus, I just took the simple approach and stuck two connectors on the board. I was planning on using proper connectors with the notch for keying instead of just the pin headers you see on the picture, but the space is too tight for them.
Apart from power traces to the DRAM sockets and the CPU, the whole board is routed by FreeRoute. I know a lot of people would say thats a big no-no, but I simply don't have the patience to do all the routing by hand. And I am really amazed by how effective FreeRoute is. I let it complete the routing, and then let it do its optimisation for a day or so, inspected the results, fixed one trace that was routed outside one of the corner holes, crossed my fingers and sent the design off for production.
There is one error on the board: The 74LS245's are flipped direction-wise, requiring two trace cuts and an extra inverted RW signal from the CPLD (see the picture of the bottom of the board).
/Tobias
|
|
|
|
|
|
Re: Jackalope Progress [message #10498 is a reply to message #9512] |
Sun, 12 November 2023 04:15 |
lynchaj
Messages: 1017 Registered: June 2016
|
Senior Member |
|
|
Speaking of old designs to revisit (see the recent N8 question); has anyone given any consideration to reviving the Jackalope 68030 project? I've always thought Jacklope had a lot of promise but it rather lost its way when Dave (aka Yoda) got sick and passed away (RIP). Still, all the design information is here and it is practically done. 68030, Ethernet, video, CPLD, it has all the good stuff just looking for some ambitious person to reclaim it and make it great.
Good luck! Andrew Lynch
|
|
|