| pdp-10 fpga [message #5326] |
Mon, 15 October 2018 09:23  |
bob98033_yahoo.com
Messages: 19
Registered: October 2018
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Junior Member |
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I did an inquiry with Mr. Conway if he would release the pc artwork and rom file for his PDP-10 fpga running MIT's ITS (Incompatible Timeshare System). Well not only did he send the files he sent me a set of PC blank boards ready to be stuffed! I attached the PC artwork files and ROM binary file. The ROM file is the motorola S3 format as the bin hex format is to large for some rom burner's. Note this FPGA implementation is different from other pdp fpga implementation in that it doesn't use a development board. The reason for that is the 36 bit memory. If access to 36 bit was remapped to fit in 32 bit memory the performance would be terrible. Instead five 512kbyte static rams were used to make 512k X 40 memory ( the four most significant bits always low to get 36 bits). There is no Jtag interface. Instead development was done on MAC OSX making a binary image including the code to program the FPGA plus a console program written in PDP-10 assembly. The router files are not in gerber format but in ExpressPCB format. ExpressPCB can convert the file format to gerber format for an additional cost $60 per PCB order. This project uses two PCB so two orders ($120 to convert to gerber format). I have no idea how many people would want a pdp-10 so the conversion to gerber format may not happen.
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| Re: pdp-10 fpga [message #5332 is a reply to message #5326] |
Mon, 15 October 2018 12:39  |
zamp
Messages: 19
Registered: April 2017
Location: Finger Lakes, NY, USA
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bob98033_yahoo.com wrote on Mon, 15 October 2018 12:23I did an inquiry with Mr. Conway if he would release the pc artwork and rom file for his PDP-10 fpga running MIT's ITS (Incompatible Timeshare System).
Is this David Conroy's FPGA PDP-10? The only real writeup I've seen on it is at http://www.fpgaretrocomputing.org/pdp10x/.
Have you come across any additional information on this FPGA PDP-10? Unless there have been new developments, David was running a version of ITS that he had to modify to use the disk-on-module and serial interfaces that he was using in his PDP-10 clone. Do you know if David has shared his changes to ITS that let it work with his clone?
The idea of building a PDP-10 clone is pretty interesting. If an OS to run on it was available, I'd probably want to build one.
Ron
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| Re: pdp-10 fpga [message #5387 is a reply to message #5386] |
Mon, 22 October 2018 14:01 |
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will
Messages: 213
Registered: October 2015
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Senior Member |
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Ah maybe the PCB was designed for reflow soldering (you're approaching the limits of my SMD knowledge!). I'm guessing the idea was to put solder paste on the board with a mask or with a syringe, then pop the chip on top, then heat up the whole ensemble.
The PCB doesn't look too horrendously complicated -- maybe you could just make a new version in KiCAD with pads suitable for hand soldering and send it off to a prototyping service which would make boards with a soldermask for you?
[Updated on: Mon, 22 October 2018 14:01] Report message to a moderator |
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| Re: pdp-10 fpga [message #5561 is a reply to message #5440] |
Tue, 20 November 2018 11:03 |
ale500
Messages: 44
Registered: April 2018
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I got today a SDRAM controller in verilog working, at least in the simulator. The pdp10x simulates without problems too. My target will be the Spartan6 on the board I posted about earlier. As soon as something works I'll poste it in the wiki page, maybe we can build something around a cheaper setup. The boards you got (or are going to get are sitting in the states aren't they ?, postage and tax would probably cost as much as ordering new sets from some smart prototypes or similar... I think.
[Updated on: Tue, 20 November 2018 11:04] Report message to a moderator |
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| Re: pdp-10 fpga [message #5944 is a reply to message #5689] |
Sat, 09 February 2019 08:53 |
djmartins
Messages: 40
Registered: February 2018
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I have a MiSTer board and this would make a great core for it!
It already has the MultiComp and a PDP-1 on it and a lot of other cores.
The dev would need to release the FPGA source code though, or write a core for MiSTer.
[Updated on: Sat, 09 February 2019 08:56] Report message to a moderator |
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| Re: pdp-10 fpga [message #6437 is a reply to message #5944] |
Wed, 07 August 2019 05:00 |
gerryk
Messages: 16
Registered: February 2017
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Junior Member |
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I am looking at how feasible this might be. One thing that will definitely need some thought is how to handle the RAM.
RAM on the MISTer is a single SDRAM module... probably 32bit. The RAM for the PDP10/x is 5x512k SRAM modules, set up so that the 40 data bits are provided by the 5 modules directly map to the 36 bits required by the PDP10/x, with the high 4 bits pulled low. This approach would not be possible in the SDRAM module, since there are only 32 data bits, so some code or other translation would be needed to handle the 1 PDP word -> 2 SDRAM word alignment.
Alternatively, a similar SRAM module could be made up to provide the necessary RAM in the same way that Dave Conway has implemented it.
Ok, just saw this:
I got today a SDRAM controller in verilog working, at least in the simulator. The pdp10x simulates without problems too. My target will be the Spartan6 on the board I posted about earlier. As soon as something works I'll poste it in the wiki page, maybe we can build something around a cheaper setup. The boards you got (or are going to get are sitting in the states aren't they ?, postage and tax would probably cost as much as ordering new sets from some smart prototypes or similar... I think.
// Gerry
[Updated on: Wed, 07 August 2019 05:12] Report message to a moderator |
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, if at all possible.
. There are nice Spartan 6 modules (from aliexpress) with a 16 k LE fpga and enough pins for the RAM and IDE, I think. One could use that, the baords are like 17 € or so.
. Guess JLCPCB decided I needed a little bit more challenge when assembling the board. The silkscreen is clearly there on the Gerber viewer on their website, so I guess this is some sort of production mistake.
