RetroBrew Computers Forum: General Discussion

Home » RBC Forums » General Discussion » Neat '040 boot ROM setup

Show: Today's Messages :: Show Polls :: Message Navigator

Neat '040 boot ROM setup [message #10552]

Sun, 24 December 2023 18:28

mikesmith
Messages: 80
Registered: March 2018

Member

Maybe relevant to the discussion a little while back about the complexities of booting the '040, this is a snippet from the schematic of a board I've been reverse-engineering this weekend. IOCLK is 25MHz in this case (same as BCLK, but possibly half a PCLK phase ahead). ROM_TA is an input to a GAL that generates TA/TBI (the '040 version of DTACK and the burst-suppression signal). It took a little while to realize what I was looking at, as the Cypress PROM is the same size/shape as a PLA...

Attachment: Screenshot 2023-12-24 at 6.21.06 PM.png
(Size: 60.79KB, Downloaded 75 times)

Report message to a moderator

Re: Neat '040 boot ROM setup [message #10553 is a reply to message #10552]

Tue, 26 December 2023 04:52

plasmo
Messages: 877
Registered: March 2017
Location: New Mexico, USA

Senior Member

I designed a 68040 flight computer 30+ years ago. Memory has faded, but the challenge I remembered the most was heat management of the 68040--it was a real power hog and avionics were limited to conduction cooling. In bench testings we didn't want to deal with revolving fan so we'd placed a water bag over 68040. That arrangement may work in the hobbyist's setup.

I'm inclined to use CF as the bootstrap device. It is 16-bit wide so its width can be doubled to 32-bit with two 74273; it is easy to remove the CF to reprogrammed it with workstation; and CF also serves as the mass storage for 68040 computer.

Static RAM is the simplest and fastest memory, but 512Kx4 is hardly enough for a decent operating system. I guess 64M is the minimal memory size, so it is DRAM in form of 72-pin SIMM or later generation memory sticks. SIMM72 and socket are pretty inexpensive and easy to find, but faster DIMM have so many different flavors that a reliable source may be hard to find.
Bill

[Updated on: Tue, 26 December 2023 04:53]

Report message to a moderator

Re: Neat '040 boot ROM setup [message #10554 is a reply to message #10553]

Wed, 27 December 2023 08:35

mikesmith
Messages: 80
Registered: March 2018

Member

As an OS / firmware developer, the most important thing to me is minimizing the overhead involved in the edit/load/debug cycle. 8-bit boot ROMs are interesting because nobody makes a 16 or 32-bit EPROM emulator. Once the ROM is debugged, I want a way to get the OS bits onto the device quickly without having to sneakernet disks around my office / desk.

I'm trying to get my hands on some of the WiFi-enabled CF cards to see if they can be used for this...

Report message to a moderator

Re: Neat '040 boot ROM setup [message #10594 is a reply to message #10552]

Mon, 05 February 2024 18:28

mikesmith
Messages: 80
Registered: March 2018

Member

For completeness' sake, here are the equations out of U11 in the schematic I posted above.

chip U11 PAL22V10

IOCLK=1
RSTI=2
TS_NORMAL=3
A30=4
IOCLK2=8
IOCLK4=9
IOCLK8=10
IOCLK16=11
ROM_NEXT=14
ROM_OE=15
ROM3_STB=16
ROM2_STB=17
ROM1_STB=18
f19=19
f20=20
f21=21
ROM_TA=23

equations

ROM_TA.oe = vcc
f21.oe = vcc
f20.oe = vcc
f19.oe = vcc
ROM1_STB.oe = vcc
ROM2_STB.oe = vcc
ROM3_STB.oe = vcc
ROM_OE.oe = vcc
ROM_NEXT.oe = vcc

global.re = /RSTI

ROM_TA := /IOCLK2 * IOCLK4 * IOCLK8 * ROM_NEXT * IOCLK16
f21 := ROM_TA * f20
    + f21
f20 := ROM_TA
    + f20
f19 := ROM_TA
ROM1_STB := IOCLK2 * /IOCLK4 * /IOCLK8 *  IOCLK16
ROM2_STB := IOCLK2 * /IOCLK4 *  IOCLK8 * /IOCLK16
ROM3_STB := IOCLK2 * /IOCLK4 * /IOCLK8 * /IOCLK16
/ROM_OE = ROM_NEXT
ROM_NEXT = RSTI * TS_NORMAL * /f21
    + RSTI * TS_NORMAL * A30
    + RSTI * /f21 * /f19 * ROM_NEXT
    + RSTI * A30 * /f19 * ROM_NEXT

Report message to a moderator

Re: Neat '040 boot ROM setup [message #10595 is a reply to message #10594]

Tue, 06 February 2024 03:50

plasmo
Messages: 877
Registered: March 2017
Location: New Mexico, USA

Senior Member

Thanks. I'll need to do similar thing with CF bootstrapping scheme. After reset, a state machine will initialize the CF to read the master boot record which will stuff 256 16-bit words into the CF's read FIFO, then MBR contents are read out where high word is latched with 2x 74273 and low word is presented directly to 68040. So two CF reads to assemble a long word instruction for 68040 to execute. Instruction stream of 128 long-word should be enough to form a small bootstrap in RAM that can load additional programs from CF disk. The same CF can serve as 68040's mass storage during normal operation.

I think it is possible to build a 68040 SBC on 100x100mm pc board with CF bootstrapping scheme; the board contains 68040, CF interface, 2x 74273, CPLD, 16/64MB SIMM72 memory stick, and OX16C954 for quad serial port.
Bill

Report message to a moderator

Re: Neat '040 boot ROM setup [message #10596 is a reply to message #10595]

Tue, 06 February 2024 09:58

mikesmith
Messages: 80
Registered: March 2018

Member

CF memory mode (presuming the card supports it) would make the code marginally easier to craft (since it would permit branching), but executing off the top of a FIFO is entirely doable.

[edit: was perhaps too flippant about not caring about low physical space; some OS' are picky about that...]

[Updated on: Tue, 06 February 2024 11:04]

Report message to a moderator

Re: Neat '040 boot ROM setup [message #10597 is a reply to message #10596]

Tue, 06 February 2024 12:58

plasmo
Messages: 877
Registered: March 2017
Location: New Mexico, USA

Senior Member

If you ever run across a CF disk that supports memory mode access, I'd love to know and get my hands on one. Only mode of operation for CF disk I know of is the FIFO mode.

In early days of Tiny68K development, I had a 68000 bootstrap out of CF disk like what I've planned for 68040. I'll dig up the design again, but 68000 and 68040 are two different beasts. --Bill

Edit, hmm, now I wonder whether I can build a simpler 68000 with just 68000, x16 DRAM, CPLD, and CF. Bootstrap off CF, DRAM controller in CPLD and serial port in CPLD. That's entirely possible. sigh, another project...

[Updated on: Tue, 06 February 2024 13:01]

Report message to a moderator

Previous Topic:	CB030, A 68030 SBC for hobbyists
Next Topic:	Bruce Culbertson NS32016 project

-=] Back to Top [=-

[ Syndicate this forum (XML) ] [

] [

]

Current Time: Mon Apr 29 13:37:20 PDT 2024

Total time taken to generate the page: 0.00743 seconds