R0  R1  R2  R3  R4  R5  R6  R7
 mov	psw,xxx00xxxb		;select RB#0	with R0:R7	mapped to -> 00:07h	RB#0 [00][01][02][03][04][05][06][07]
 mov	psw,xxx01xxxb		;select RB#1	with R0:R7	mapped to -> 08:0Fh	RB#1 [08][09][0A][0B][0C][0D][0E][0F]
 mov	psw,xxx10xxxb		;select RB#2	with R0:R7	mapped to -> 10:17h	RB#2 [10][11][12][13][14][15][16][17]
 mov	psw,xxx11xxxb		;select RB#3	with R0:R7	mapped to -> 18:1Fh	RB#3 [18][19][1A][1B][1C][1D][1E][1F]

BAD:	push	Acc		;2b2c	; save Acc value on the stack (direct addressing access: SFR 'Acc')
	...
	pop	Acc		;2b2c	; restore Acc value off the stack (direct addressing access: SFR 'Acc')
Bad Total:			;4b4c	; TOTAL

GOOD:	mov	R2,a		;1b1c	; save Reg A value to R2
	...
	mov	a,R2		;1b1c	; restore Reg A value from R2
GOOD Total:			;2b2c	; TOTAL

 ________________________ARITHMETIC OPERATIONS___________________________________________________
| Mnemonic             | Description                                            | Bytes | Cycles |
|______________________|________________________________________________________|_______|________|
| REGISTER ADDRESSING: |                                                        |       |        |
| add  | A,Rn          | Add register to Accumulator                            |   1   |   1    |
| addc | A,Rn          | Add register to Accumulator with Carry                 |   1   |   1    |
| subb | A,Rn          | Subtract register from Accumulator with Borrow         |   1   |   1    |
| inc  | Rn            | Increment Register                                     |   1   |   1    |
| dec  | Rn            | Decrement Register                                     |   1   |   1    |
| INDIRECT ADDRESSING: |                                                        |       |        |
| add  | A,@Ri         | Add indirect RAM to Accumulator                        |   1   |   1    |
| addc | A,@Ri         | Add indirect RAM to Accumulator with Carry             |   1   |   1    |
| subb | A,@Ri         | Subtract indirect RAM from Accumulator with Borrow     |   1   |   1    |
| inc  | @Ri           | Increment indirect RAM                                 |   1   |   1    |
| dec  | @Ri           | Decrement indirect RAM                                 |   1   |   1    |
|______|_______________|________________________________________________________|_______|________|

 ________________________LOGICAL OPERATIONS______________________________________________________
| Mnemonic             | Description                                            | Bytes | Cycles |
|______________________|________________________________________________________|_______|________|
| REGISTER ADDRESSING: |                                                        |       |        |
| anl  | A,Rn          | And register to Accumulator                            |   1   |   1    |
| orl  | A,Rn          | Or register to Accumulator                             |   1   |   1    |
| xrl  | A,Rn          | Exclusive-Or register to Accumulator                   |   1   |   1    |
| INDIRECT ADDRESSING: |                                                        |       |        |
| anl  | A,@Ri         | And indirect RAM to Accumulator                        |   1   |   1    |
| orl  | A,@Ri         | Or indirect RAM to Accumulator                         |   1   |   1    |
| xrl  | A,@Ri         | Exclusive-Or indirect RAM to Accumulator               |   1   |   1    |
|______|_______________|________________________________________________________|_______|________|

 ________________________DATA TRANSFER___________________________________________________________
| Mnemonic             | Description                                            | Bytes | Cycles |
|______________________|________________________________________________________|_______|________|
| REGISTER ADDRESSING: |                                                        |       |        |
| mov  | A,Rn          | Move Register to Accumulator                           |   1   |   1    |
| mov  | Rn,A          | Move Accumulator to Register                           |   1   |   1    |
| mov  | Rn,direct     | Move direct byte to Register                           |   2   |   1    |
| mov  | Rn,#data      | Move immediate data to Register                        |   2   |   1    |
| mov  | direct,Rn     | Move Register to direct byte                           |   2   |   2    |
| xch  | A,Rn          | Exchange Register with Accumulator                     |   1   |   1    |
| INDIRECT ADDRESSING: |                                                        |       |        |
| mov  | A,@Ri         | Move indirect RAM to Accumulator                       |   1   |   1    |
| mov  | direct,@Ri    | Move indirect RAM to direct byte                       |   2   |   2    |
| movx | A,@Ri         | Move external RAM (8-bit addr) to Accumulator          |   1   |   2    |
| movx | @Ri,A         | Move Accumulator to external RAM (8-bit addr)          |   1   |   2    |
| xch  | A,@Ri         | Exchange indirect RAM with Accumulator                 |   1   |   1    |
| xchd | A,@Ri         | Exchange low-order digit indirect RAM with Accumulator |   1   |   1    |
|______|_______________|________________________________________________________|_______|________|

 ________________________PROGRAM BRANCHING_______________________________________________________
| Mnemonic             | Description                                            | Bytes | Cycles |
|______________________|________________________________________________________|_______|________|
| REGISTER ADDRESSING: |                                                        |       |        |
| cjne | Rn,#data,rel  | Compare Immediate to Register and jump if not equal    |   3   |   2    |
| djnz | Rn,rel        | Decrement Register and jump if not zero                |   2   |   2    |
|      |               |                                                        |       |        |
| INDIRECT ADDRESSING: |                                                        |       |        |
| cjne | @Ri,#data,rel | Compare Immediate to indirect and jump if not equal    |   3   |   2    |
|______|_______________|________________________________________________________|_______|________|

		;-----------------------; RB#0 is active from the calling routine
		; RB#0 Ram Addresses	; NOTE: none of these registers are changed by the subroutine.
		; RB#0+R0->00h  [ ]	; 
		; RB#0+R1->01h  [ ]	;
		; RB#0+R2->02h  [ ]	;
		; RB#0+R3->03h  [ ]	;
		; RB#0+R4->04h  [ ]	;
		; RB#0+R5->05h  [ ]	;
		; RB#0+R6->06h  [ ]	;
		; RB#0+R7->07h  [ ]	;
		;-----------------------; for clarity, interrupt enable/disable code is removed
Subroutine+Register_Bank:		;
		;-----------------------; 
Line1:	mov	17h,psw		;3b2c	; save the calling routine's psw in direct address of 17h=RB#2+R7
Line2:	mov	16h,a		;3b2c	; save the calling routine's Reg A by direct addressing of 16h=RB#2+R6; Could delete this.
Line3:	mov	psw,#10h	;3b2c	; select RB#2, if the subroutine requires the calling routine's psw flags, use r7's image
		;-----------------------; the calling routine can restore Reg A (if it was saved) by direct addressing: mov a,16h
		; RB#2 Ram Addresses	; 
		; RB#2+R0->10h  [ ]	; RAM byte available to subroutine
		; RB#2+R1->11h  [ ]	; RAM byte available to subroutine
		; RB#2+R2->12h  [ ]	; RAM byte available to subroutine
		; RB#2+R3->13h  [ ]	; RAM byte available to subroutine
		; RB#2+R4->14h  [ ]	; RAM byte available to subroutine
		; RB#2+R5->15h  [ ]	; RAM byte available to subroutine
		; RB#2+R6->16h  [Reg A]	; copy of calling routine's Reg A, loaded by direct addressing 16h=RB#2+R6
		; RB#2+R7->17h  [PSW]	; copy of calling routine's PSW flags and register bank loaded by direct addressing 17h=RB#2+R7
;---------------;-----------------------;
; subroutine code here			;
;---------------;-----------------------;
	mov	a,result		; subroutine passes the result back to the calling routine in Reg A
;---------------;-----------------------; if the calling routine wants to recover its Reg A, use direct addressing: mov a,16h
Line4:	mov	psw,r7		;2b2c	; restore the calling routine's flags and register bank from the subroutine's R7
	ret	;-----------------------; RB#0 is now active
		; RB#0 Ram Addresses	; NOTE: none of these registers are changed by the subroutine.
		; RB#0+R0->00h  [ ]	;
		; RB#0+R1->01h  [ ]	;
		; RB#0+R2->02h  [ ]	;
		; RB#0+R3->03h  [ ]	;
		; RB#0+R4->04h  [ ]	;
		; RB#0+R5->05h  [ ]	;
		; RB#0+R6->06h  [ ]	;
		; RB#0+R7->07h  [ ]	;
		;-----------------------;

		;-----------------------;---------------; one bank among RB#{0,1,2} is now active in foreground
		; RB#{0:2} Ram Addresses		; NOTE: none of these registers are changed by the subroutine.
		; RB#{0:2}+R0->{00h,08h,10h}  [ ]	;
		; RB#{0:2}+R1->{01h,09h,11h}  [ ]	;
		; RB#{0:2}+R2->{02h,0Ah,12h}  [ ]	;
		; RB#{0:2}+R3->{03h,0Bh,13h}  [ ]	;
		; RB#{0:2}+R4->{04h,0Ch,14h}  [ ]	;
		; RB#{0:2}+R5->{05h,0Dh,15h}  [ ]	;
		; RB#{0:2}+R6->{06h,0Eh,16h}  [ ]	;
		; RB#{0:2}+R7->{07h,0Fh,17h}  [ ]	;
		;-----------------------;---------------;
ISR+Register_Bank:			; for clarity, interrupt enable/disable code is removed
		;-----------------------; the following saves the foreground for restoration before 'reti'
Line1:	mov	1Fh,psw		;3b2c	; save foreground's psw by direct address of 1Fh=RB#3+R7
Line2:	mov	1Eh,a		;3b2c	; save the foreground's Reg A by direct addressing of 1Eh=RB#3+R6
Line3:	mov	psw,#18h	;3b2c	; select RB#3, if the ISR requires the foreground's psw flags, use r7's image
		;-----------------------;
		; RB#3 Ram Addresses	; RB#3 is now active, with R7 and R6 already loaded with restoration values
		; RB#3+R0->18h  [ ]	; RAM byte available to the ISR
		; RB#3+R1->19h  [ ]	; RAM byte available to the ISR
		; RB#3+R2->1Ah  [ ]	; RAM byte available to the ISR
		; RB#3+R3->1Bh  [ ]	; RAM byte available to the ISR
		; RB#3+R4->1Ch  [ ]	; RAM byte available to the ISR
		; RB#3+R5->1Dh  [ ]	; RAM byte available to the ISR
		; RB#3+R6->1Eh  [Reg A]	; foreground's Reg A stored here
		; RB#3+R7->1Fh  [PSW]	; foreground's PSW flags and Register Bank selection stored here
;---------------;-----------------------; the ISR's RB#3.R0:R7 RAM bytes don't affect the foreground
; interrupt service routine code here	;
;---------------;-----------------------; now fully restoring foreground:
Line4:	mov	a,r6		;1b1c	; restore foreground Reg A from R6
Line5:	mov	psw,r7		;2b2c	; restore foreground flags and register bank from R7.
	reti			;	; foreground register bank is now active, return from ISR
		;-----------------------;---------------; foreground is fully restored
		; RB#{0:2} Ram Addresses		; NOTE: none of these registers are changed by the ISR.
		; RB#{0:2}+R0->{00h,08h,10h}  [ ]	;
		; RB#{0:2}+R1->{01h,09h,11h}  [ ]	;
		; RB#{0:2}+R2->{02h,0Ah,12h}  [ ]	;
		; RB#{0:2}+R3->{03h,0Bh,13h}  [ ]	;
		; RB#{0:2}+R4->{04h,0Ch,14h}  [ ]	;
		; RB#{0:2}+R5->{05h,0Dh,15h}  [ ]	;
		; RB#{0:2}+R6->{06h,0Eh,16h}  [ ]	;
		; RB#{0:2}+R7->{07h,0Fh,17h}  [ ]	;
		;-----------------------;---------------;