ld      a, %00000101            ; point to WR5
        out     (SIO_CTRL_A), a         ; send pointer to channel a
        ld      a, %11101010            ; enable the RTS bit
        out     (SIO_CTRL_A), a         ; send the updated register

=====================
CURRENT CODE LISTING:
=====================
SIO_PORT_A_WRITE:
        pop     bc                      ; Return Address is first off the stack
        pop     de                      ; Character stored in e
        push    bc                      ; Restore the return address to the stack for ret
        push    af                      ; save af register
        ld      a, e                    ; move the character to A
        out     (SIO_DATA_A), a         ; send the character to the SIO
        call    SIO_A_TX_WAIT           ; block until the character is sent
        pop     af                      ; restore af register
        ret
=====================
STREAMLINED CODE LISTING:
=====================
SIO_PORT_A_WRITE:			; NOTE STACK ACTIVITY IS SLOW... AVOID WHEN OK
        push    af                      ; save af register
                                        ; Character stored in e
        ld      a, e                    ; move the character to A
        out     (SIO_DATA_A), a         ; send the character to the SIO
        call    SIO_A_TX_WAIT           ; block until the character is sent
        pop     af                      ; restore af register
        ret

; Initialize SIO
INIT_SIO:                               ; QUICKLY RESET SIO SO INTERRUPTS DISABLED, THEN INIT
        push    af                      ; push the af register [STACK+AF]
        ld      a, %00011000            ; store channel reset command in a
        di                              ; disable Z80 interrupt activity while resetting SIO{A,B}
        out     (SIO_CTRL_A), a         ; reset SIO Channel A, interrupts disabled
        out     (SIO_CTRL_B), a         ; reset SIO Channel B, interrupts disabled
        ei                              ; enable Z80 interrupt activity
        ;-------------------------------; INITIALIZE SIO{A&B}
        push    bc                      ; push the bc register [STACK+AFBC]
        push    hl                      ; push the hl register [STACK+AFBCHL]
        ;
        ; REMEMBER SIO MUST INITIALIZE WR5 FIRST!!
        ;
        ; To receive or transmit data in the Asynchronous mode, the Z80 SIO must
        ; be initialized with the following parameters: character length, clock rate,
        ; number of stop bits, even or odd parity, interrupt mode, and receiver or
        ; transmitter enable.
        ;
        ld      a, CONF_STR_N           ; load the number of config strings to a
        ld      hl, SIO_INIT_STR        ; port first

CONFIG_LOOP:
        ld      c, (hl)                 ; address of SIO port in c
        inc     hl                      ; point at the length
        ld      b, (hl)                 ; length of byte string
        inc     hl                      ; point at the bytestring
        otir                            ; send bytes
        dec     a                       ; decrement our counter and set flags
        jr      nz, CONFIG_LOOP         ; jump back to the loop if not

        pop     hl                      ; pop hl [STACK+AFBC..]
        pop     bc                      ; pop bc [STACK+AF..]
        pop     af                      ; pop af [STACK+..]

        ret                             ; return

;--------------------------------------------------------------------
; alternate 1:				; B   T   D; B is bytes of code, T is T-states, D is disabled duration T-states
	di				; 1   4   0;
	ld	a, %00000101		; 2   7   7; point to WR5
	out	(SIO_CTRL_A), a		; 2  11  11; send pointer to channel a
	ld	a, %11101010		; 2   7   7; enable the RTS bit
	out	(SIO_CTRL_A), a		; 2  11  11; send the updated register
	ei				; 1   4   4; intr off for 40 T-states
;					;==  ==  ==					 
;				Totals	 10B,44T,40T :: Interrupts disabled for a duration of 40 T-states.
;--------------------------------------------------------------------
; alternate 2:				; B   T   D; B is bytes of code, T is T-states, D is disabled duration T-states
	ld	a, %00000101		; 2   7   0; point to WR5
	di				; 1   4   0;
	out	(SIO_CTRL_A), a		; 2  11  11; send pointer to channel a
	ld	a, %11101010		; 2   7   7; enable the RTS bit
	out	(SIO_CTRL_A), a		; 2  11  11; send the updated register
	ei				; 1   4   4; intr off for 33 T-states
;					;==  ==  ==					 
;				Totals	 10B,44T,33T  :: Interrupts disabled for a duration of 33 T-states.
;--------------------------------------------------------------------
; SPOILER ALERT: alternates 3&4 are equivalent, tiebreaker: alternate 3 wins on better documentation (binary values)
; alternate 3:				; B   T   D; B is bytes of code, T is T-states, D is disabled duration T-states
	ld	a, %00000101		; 2   7   0; point to WR5
	ld	b, %11101010		; 2   7   0; enable the RTS bit
	di				; 1   4   0;
	out	(SIO_CTRL_A), a		; 2  11  11; send pointer to channel a
	ld	a,b			; 1   4   4; enable the RTS bit
	out	(SIO_CTRL_A), a		; 2  11  11; send the updated register
	ei				; 1   4   4; intr off for 30 T-states
;					;==  ==  ==					 
;				Totals	 11B,48T,30T :: Interrupts disabled for a duration of 30 T-states.
;--------------------------------------------------------------------
; SPOILER ALERT: alternates 3&4 are equivalent, tiebreaker: alternate 4 loses on lesser documentation (hex values) 
; alternate 4:				; B   T   D; B is bytes of code, T is T-states, D is disabled duration T-states
	ld	hl, $05EA		; 3  10   0; point to WR5, then enable the RTS bit
	ld	a,h			; 1   4   0;
	di				; 1   4   0;
	out	(SIO_CTRL_A), a		; 2  11  11; send pointer to channel a
	ld	a,l			; 1   4   4; enable the RTS bit
	out	(SIO_CTRL_A), a		; 2  11  11; send the updated register
	ei				; 1   4   4; intr off for 30 T-states
;					;==  ==  ==					 
;				Totals	 11B,48T,30T :: Interrupts disabled for a duration of 30 T-states.
;--------------------------------------------------------------------
; 30T-states with interrupt disbled, equivalent to alternates 3&4 but cost one byte more.
; alternate 5:				; B   T   D; B is bytes of code, T is T-states, D is disabled duration T-states
	ld	a, %11101010		; 2   7   0; enable the RTS bit
	ex	af,af'			; 1   4   0;
	ld	a, %00000101		; 2   7   0; point to WR5
	di				; 1   4   0;
	out	(SIO_CTRL_A), a		; 2  11  11; send pointer to channel a
	ex	af,af'			; 1   4   4;
	out	(SIO_CTRL_A), a		; 2  11  11; send the updated register
	ei				; 1   4   4; intr off for 30 T-states
;					;==  ==  ==					 
;				Totals	 11B,49T,30T :: Interrupts disabled for a duration of 30 T-states.
;--------------------------------------------------------------------
; THE REAL WINNER!!!! 28T-states
; alternate 6:				; B   T   D; B is bytes of code, T is T-states, D is disabled duration T-states
	ld	hl, $05EA		; 3  10   0; point to WR5, then enable the RTS bit
	ld	c,SIO_CTRL_A		; 2   7   0; point to the sio.a.control register
	di				; 1   4   0;
	out	(c),h			; 2  12  12;
	out	(c),l			; 2  12  12;
	ei				; 1   4   4; intr off for 28 T-states
;					;==  ==  ==					 
;				Totals	 11B,49T,28T :: Interrupts disabled for a duration of 28 T-states.
;--------------------------------------------------------------------

;j: at 0000h
RST0:					;j: FOR A BETTER CHANCE OF CAPTURING RUNAWAY CODE AND REINITIALIZING AT 0003h
	nop			;@0000h	;j: if runaway code rolls from top of memory into 0000h address...
	nop			;@0001h	;j: after a last instruction framed from @{FFFC,FFFD,FFFE,FFFFh}...
	nop			;@0002h	;j: it will be assured to be in-sync with opcode instruction by 0003h
					;j: bytes of single instruction can be {4,3,2,1} byte(s) long
					;j: worst case is 4 byte long instruction fetched at FFFF,0000,0001,0002h)

        di                      ;@0003h	; disable interrupts to start off
        jp      START                   ; jump over the reset handlers and IVT
...
;j: at 0200h+
START:
					;j: If I recall, its true that ld SP $0000 will make the actual top of stack occur at $FFFF
					;j: as it decrements the stack address before pushing the first data onto the stack.
	;See page 25, Z80 Tech Manual	;j: PUSH HL acts like:	a) dec SP	;SP was 0000h, then 0000h -1 = FFFFh
					;j:			b) LD (SP),(H)	;LD (FFFFh),(H)
					;j:			c) dec SP	;SP was FFFFh, then FFFFh -1 = FFFEh
					;j:			d) LD (SP),(L)	;LD (FFFEh),(L)
					;j:
					;j: POP HL acts like:	a) LD (L),(SP)	;SP is FFFEh, value in FFFEh copied into reg L
					;j:			b) inc SP	;SP was FFFEh, then FFFEh +1 = FFFFh
					;j:			c) LD (H),(SP)	;SP is FFFFh, value in FFFFh copied into reg H
					;j:			d) inc SP       ;SP was FFFFh, then FFFFh +1 = 0000h
					;j:
					;j: Note: the stack never 'uses' 0000h for data UNLESS you pop it beyond your push count
					;j: or RET from subroutines more times than you called subroutines
					;j:
					;j: When you POP data, the SP is already pointing at the LOW BYTE
					;j: coders figure this out when they debug their stack and are surprised
;j:	ld	sp, $0000		;j: would be the pro way to initializing, but only *IF* you have RAM at FFFFh :)

        ld      sp, $FFFF               ; set the stack pointer
        im      2                       ; interrupt mode 2
        ld      a, INT_TABLE/256        ; store the MSB of the IVT addr in a
        ld      i, a                    ; load a to i

					;j: at this point there are no register values to save, so no need to PUSH/POP them in INIT_SIO

        call    INIT_SIO                ; set up the SIO
	call	STARTUP_MESSAGE		; send the startup message

        ei                              ; enable interrupts
...

;
; Routine to send the startup message to Port A of the SIO
; Must call INIT_SIO first!
;

STARTUP_MESSAGE:

;j: no need for these PUSHes and POPs before returning. As the code grows, that may change.
;j: however the more you can eliminate unnecessary stack activity, the faster the code will run.
;j: in interrupt service routines its best to minimize internal CALL&RET / PUSH&POP unless protecting the registers you change.
;j: ISR PUSH&POP minimization often change registers you might use; if you PUSH BC for B only, you get C register for 'free'.
;j: and all ISRs would need to PUSH AF on entry and POP AF before return. Avoid another level of PUSH&POP AF. Use a free register 

	push	af			; save af register
	push	bc			; save bc register
	push	hl			; save hl register
        ld      hl, STARTUP_STR         ; load the address of the startup string to hl
STARTUP_MESSAGE_LOOP:
        ld      a, (hl)                 ; load the first char to a
        or      a                       ; is it a NULL?
        jr      z, MESSAGE_LOOP_END     ; we're done if it is

;j: no need of register B because you don't need to PUSH BC
;j: and if you need to PUSH a single register of a register pair, its not necessary to change modify that register.
;j: A PUSH BC takes 11 T-states, a POP takes 10. But register loads from regisers are the fastest. LD E,C takes 4 T-states.
;j: If register E isn't used, you can LD E,C in only 4 T-states and call a routine that changes C without PUSH&POP
;j: where possible, that it better, but it might bite you when you rewrite a routine to add more features.
;j: Its a good idea to document which registers some subroutines change. It reduces debugging time.
;j: If code requires a register be unchanged before calling a subroutine, document that before the CALL. Helps debugging.

	ld      b, 0                    ; not a NULL, zero out b

        ld      c, a                    ; store our char in c

;j: this PUSH is a BUG because will cause a STACK overrun and mess up pops and returns immediately
;j: no need to push a character on the stack, if you need to save it, copying it to an unused register or ram, is faster

	push    bc                      ; put the char on the stack

        call    SIO_PORT_A_WRITE        ; call the write routine; 
        inc     hl                      ; point to the next char in the string
        jr      STARTUP_MESSAGE_LOOP    ; back to the beginning of the loop

MESSAGE_LOOP_END:

;j: no need for these PUSHes and POPs before returning. As the code grows, that may change.
;j: when you're doing an initial debug, optional clutter like this becomes additional code you have to consider as being the bug.

	pop	hl			; restore hl register
	pop	bc			; restore bc register
	pop	af			; restore af register

	ret

;
; handler for unimplemented ISRs
;

NO_ISR:
        ei                              ; enable interrupts

;j: RETI is only used as a RET for interrupt triggered CALLs
;j: This might create a interrupt mess. RET is the instruction to use here.

        reti                            ; go back to what we were doing

        SECTION DATA

STARTUP_STR:
        db      "PZ803 ROMMon v0.1\r\n"
        db      "(c) 2023 - Peter H. Ezetta\r\n", 0

        out     (SIO_DATA_A), a         ; send the character to the SIO
        call    SIO_A_TX_WAIT           ; block until ***this*** character is sent
 

        call    SIO_A_TX_WAIT           ; block until the ***previous*** character has completed
        out     (SIO_DATA_A), a         ; send the character to the SIO and get on with your day...