| introducing duodyne retrocomputer [message #10376] |
Tue, 22 August 2023 04:46  |
lynchaj
Messages: 1080
Registered: June 2016
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Senior Member |
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Hi
A small team and myself have been working on a third generation ROMWBW focused retrocomputer incorporating lessons learned and improvements from my original ECB Z80 SBC (aka N8VEM) and the nhyodyne modular computer. It is literally designed around ROMWBW from the start for a robust OS and software environment.
Duodyne is a new design which integrates many functions into larger, modular boards on a backplane. The intent is to create a powerful and capable system like an SBC, but with modularity and an expandable backplane. There is plenty of room for those larger projects like uPD7220 GDCs, 32-bit CPUs, graphics boards, etc.
Generally speaking, the design approach packs more functionality onto fewer, larger boards to increase component sharing and reduce overall the number of boards. The whole system is open source and freely available on GitHub.
https://github.com/lynchaj/duodyne
The minimum core system is 3 boards: a 4-slot backplane, a Z80 processor, and a ROMRAM board.
The Z80 processor board has a Z80 CPU, dual DMAs (derived from Wolfgang's ECB DMA), onboard 16C550 UART, and I2C channel. It also features an improved memory mapper from Sergey's Zeta project with extended memory addressing. No more clunky latches on the memory boards!
The ROMRAM board is an 8-bit memory board with up to 4MB of any combination of 512KB Flash ROM or SRAM. Plus, it includes a real-time clock, user LEDs and button, plus 4 serial I2C memory sockets.
The initial build and test have gone well, and all the systems appear to be working nominally. There were some findings, and I am planning to do PCB respins after testing finishes.
If you think you would be interested in building your own duodyne please reply here, send me an email, PM, or on the GitHub so you can be contacted.
Thank you and have a nice day. Andrew Lynch
PS, many more boards are planned and there is a template available for you to design your own. Also, a prototyping board for real-time experimenting. You can order your own PCBs or wait for group purchases as you see fit.
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| Re: introducing duodyne retrocomputer [message #10385 is a reply to message #10383] |
Thu, 24 August 2023 09:56  |
lynchaj
Messages: 1080
Registered: June 2016
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Senior Member |
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Hi
Originally, I considered making it like a VME board to leverage surplus card cages but decided against it because of the DIN 41612 connectors and possible confusion of trying to use a duodyne board in a VME backplane. They are also double-wide Euro cards like double-wide ECB.
We made some double-wide ECB boards (6x0x and N8, if I recall) and they worked alright. I was looking for a larger bus (150 pins) with plenty of VCC and GND pins plus lesser used but convenient voltages like +12V and -12V. It's ready for expansion with full 32-bit address and data paths plus additional control signals for Motorola 68K style and Intel 8086 logic.
It is also a bit reminiscent of S-100 but without the board edge interface and funky edge connector. There are 5mm exclusion zones on each side for board guides in the chassis (planned)
Thanks, Andrew Lynch
[Updated on: Thu, 24 August 2023 09:56] Report message to a moderator |
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| Re: introducing duodyne retrocomputer [message #10394 is a reply to message #10392] |
Sun, 27 August 2023 04:09 |
e2k
Messages: 33
Registered: June 2021
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Member |
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lynchaj wrote on Sat, 26 August 2023 15:02
I connect to an ATX break-out board that splits the supply into +12V, -12V, 5V, and GND wires.
I thought about adding a 3.3V line but it is so easily converted from 5V that it's not worth using up space on the backplane for it.
The break-out board I was wondering about, thanks You got me on the right track, I ordered some for my projects ...
And, I think 3v3 to have is nice, as people use than little LDOs, get heat and no idea, why they fail 
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| Re: introducing duodyne retrocomputer [message #10397 is a reply to message #10394] |
Mon, 28 August 2023 06:22 |
lynchaj
Messages: 1080
Registered: June 2016
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Senior Member |
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Hi
What I've seen so far is most boards don't need 3.3V and those that do need it require only small amounts (SD, Propeller, etc.) One board that needs 3.3V actually generates its own from 5V (ESP32) which is quite handy. If it ever gets to where we have widespread need for 3.3V it can be added using the reserved user pins on the backplane and PCB respins.
https://github.com/lynchaj/duodyne
If you or anyone else is interested in building your own duodyne please follow on the GitHub link above. Especially if you are interested in joining the initial build and test, that would be great. The risk of a total dud has been mitigated since we have made a lot of progress and shown proof of functionality. Still there is testing left to do but I think chance of unrecoverable critical flaw is now very low.
Thanks, Andrew Lynch
PS, the Gerbers are posted so you can make your own PCBs or wait for group purchase of boards
[Updated on: Mon, 28 August 2023 06:23] Report message to a moderator |
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| Re: introducing duodyne retrocomputer [message #10404 is a reply to message #10403] |
Wed, 06 September 2023 04:47 |
lynchaj
Messages: 1080
Registered: June 2016
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Senior Member |
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Hi
I am working on a tangent project called "Slick" which is an updated Z80 processor board using a pair of EPM7046S CPLDs instead of GALs and some 74xx "flip-flop" logic.
This is experimental/developmental and won't be part of the duodyne system itself but is leveraging it to help build my skill set and tools to use CPLDs.
Some upcoming duodyne board projects will almost certainly require CPLDs to function, so I need a test project as an introduction to hobbyist CPLDs.
If you are interested in following along, building your own, learning about CPLDs along with me, please let me know and I'll get you some extra PCBs.
There are many ways to do CPLDs, but it seems few open source/free alternatives exist. In this case, I am using Altera/Intel MAX 7000S devices (EPM7064S) because they are 5V capable and exist in a large package through-hole (PLCC-84). I am using Digital (FOSS) for schematic capture and Quartus for Verilog compilation/synthesis.
The plan is to use a USB Blaster clone to connect to the 10-pin JTAG port on the board (one per CPLD) for in-circuit programming. This seems to be a common, low-cost approach and we'll see how well it works. The good news is the schematic is captured in Digital, exports to Verilog, Quartus imports the Verilog files and compiles/synthesizes. Apparently, all successfully.
You can follow along here: https://github.com/lynchaj/duodyne/tree/main/Slick
Thanks, Andrew Lynch
PS, I think both CPLDs could get stuffed into a single EPM7128S in QFP-160 but that would require PCB SMT assembly of a large 160 pin package. While technically possible, it is not really suitable for a developmental system likely to require changes, cuts and jumpers, etc. I considered a QFP-160 to PGA-160 adapter board but they aren't really common and the one I could find cost $30 each plus shipping. I don't think it is really worth the extra cost and/or pain at this point.
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| Re: introducing duodyne retrocomputer [message #10407 is a reply to message #10406] |
Wed, 06 September 2023 20:20 |
plasmo
Messages: 916
Registered: March 2017
Location: New Mexico, USA
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Senior Member |
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JTAG programmer does not power the CPLD at all. In fact, JTAG programmer draws power so you'll notice greater power consumption when JTAG programmer is plugged in. CPLD pins are all weakly pulled up while being programmed, presumably this is to avoid enabling devices it controlled since most chip selects are active low. If you are concerned about devices enabled thus creating contentions while CPLD is being programmed in-situ, you can remove it and program separately. I never bother with that and seldom have problems programming the CPLD in situ.
Some designs use lots of internal macrocells and other designs are heavy on IO pins so you don't generally have a situation where both macrocells and IO pins are 100% utilize. I do have several designs where IO and macrocells are both 100% utilized, but that's because I kept adding features until I used up all IO or macrocells. You should also let Quartus assign the IO pins where possible because the router is more efficient when it has the freedom to assign pins. Of course you'll need to lock down the pin assignments when you go to actual PC board, but the initial pin assignments are likely to retain its routability when you made minor design modifications after pc board were made.
I will say that pin limitations as well as macrocell limitations are something I wrestled with ALL...THE...TIME. Design approaches changed because of these limitations. One CPLD can easily contains address decodes, memory bank select registers, ROM, serial port, I2C, timer, discrete I/O, plus more so it is complicated tradeoff between various functions and what features a function can implement. It will keep you entertained for long time!
Bill
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| Re: introducing duodyne retrocomputer [message #10408 is a reply to message #10407] |
Thu, 07 September 2023 03:53 |
lynchaj
Messages: 1080
Registered: June 2016
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Senior Member |
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Hi Bill
OK, well that's a good thing to learn. I guess my power separation jumper is now a power input for each CPLD to power its local enclave while JTAG programming. One idea I considered was just not installing any of the other chips so only the single CPLD being programmed is installed. Then there is no risk of contention between the CPLD and anything else on the board. That would remove the need for separate power enclaves for the CPLDs.
I appreciate your comments and wisdom on CPLDs especially during this learning phase. That is my goal with Slick is to try out these concepts on a fairly well-known design so later I can use CPLDs on more complex designs. I am hoping to redesign the uPD7220 GDC board using CPLDs to simplify the video memory and fix the finicky timing logic section.
If you'd like to see the design information on how I've gotten this far, I posted here on the GitHub. The schematic capture is done using Digital and then exported as Verilog. I use Quartus to import the Verilog and do the compile/synthesis. Digital is nice for schematic capture because I can reuse my designs from the GALs and consolidate them into the CPLD designs. Also there is a PNG export function so you can see what the input schematic looks like.
https://github.com/lynchaj/duodyne/tree/main/Slick/CPLDs
Thanks, Andrew Lynch
PS, there is not much left on the PCB other than the CPLDs to consolidate. There is the CPU, the DMAs, the I2C chip, the UART, and a couple ATtiny controllers for miscellaneous functions. The rest are external bus buffers/transceivers or OC outputs. I am trying to avoid putting the CPLDs directly on the external bus since it can be a difficult electrical environment. Use the buffers to filter out all that EMI/EMC junk and pass relatively clean signals.
[Updated on: Thu, 07 September 2023 03:58] Report message to a moderator |
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