Hi
Today has been a good day. Got outside, did stuff with the family, and got a chance to work on the Gryphon schematic and PCB.

Here is an updated KiCAD EDA file set to include and updated schematic and initial PCB layout. Doing the PCB layout was highly educational and I discovered numerous errors in the part footprints and in my schematic as well.

Regarding the CPLDs; since we are going down the programmable logic path anyway I have a suggestion. Rather than consolidate the 7 PALs into one CPLD how about focus on eliminating the 13 74LSxxx glue logic chips instead? If you look at the board, there are a whole bunch of miscellaneous logic chips in the center left of the board which are going to be a pain for trace routing. If you want to save PCB space take a look at them first. Maybe two CPLDs to consolidate the PALs and the 7LSxxx glue logic.

Thanks

Andrew Lynch