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Re: ECB-DMA [message #6789 is a reply to message #6788] Sat, 16 November 2019 14:02 Go to previous messageGo to previous message
wsm is currently offline  wsm
Messages: 232
Registered: February 2017
Location: AB, Canada
Senior Member
Quote:
Thank you for the explanation about CF card timing. SD cards have some slow timing requirements on start-up, although they are of a different nature.
You're welcome. As to SD, yes there's the 400KHz initialization pulses and there can also be data transfer timing issues. A 25MHz HW SPI can be slower than a 33MHz Z180 INIR instruction and I now use DMA rather than processor timing. This allows the transfer to occur as soon as the SPI interface can handle the data transfer and moves timing issues to within my CPLD.

I know I've wandered a bit off-topic but for those that don't want to dig through the ATA specification, I'm including some timing comments from an ATA CPLD that I developed and has been used successfully with CF cards, ATA hard disks and an ATA to SATA interface.

//               cycle   a_setup  rd/wr(reg)  rd/wr  wr_hold
//       PIO 0 :  600      70      290         165     30
//       PIO 1 :  383      50      290         125     20
//       PIO 2 :  330      30      290         100     15
//       PIO 3 :  180      30             80           10
//       PIO 4 :  120      25             70           10
//    CF PIO 5 :  100      15             65            5
//    CF PIO 6 :   80      10             55            5

//                    cycle   r_setup  rd/wr  wr_hold  rd_neg  wr_neg
//       DMA 0 :       480      150     215      20      50      215
//       DMA 1 :       150       60      80      15      50       50
//       DMA 2 :       120       50      70      10      25       25
//    CF DMA 3 :       100       50      65       5      25       25
//    CF DMA 4 :        80       45      55       5      20       20
 
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