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Re: ECB-DMA [message #6787 is a reply to message #6786] Sat, 16 November 2019 09:28 Go to previous messageGo to previous message
wsm is currently offline  wsm
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Registered: February 2017
Location: AB, Canada
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I use DMA extensively in my Z180 designs and etchedpixels post confirms many of the reasons why I quit using the Z80 and only ever used the Z80 DMA in one design a VERY LONG time ago. Of course the Z180 also has the convenience of integrated peripherals and higher speed Smile Since the HD64180 came out in 1985, I still consider it and it's faster cousins to be "retro".

The Z180 DMA has a major enhancement, namely 20-bit addresses which allows it to fully address 1MB of memory independent of any MMU settings. Thus it is straightforward to do I/O to/from a bank and also bank-to-bank transfers such as buffer blocking. Designs using the Z80 DMA and more than 64K could greatly benefit from using a similar technique by using external registers for DMA address bits higher than A15. The one negative is that DMA transfers wouldn't be able to span a 64K boundary but that can be overcome in SW.

I also agree that many of the ATA designs I've seen don't pay attention to the ATA specifications about timing and would be prone to failure. Interfaces like GIDE and one recently promoted on VCF simply rely on having a slow processor that doesn't exceed the PIO mode 0 timing of 290ns rd/wr pulses and 600ns cycle times ... unrealistic on something like a 20MHz Z80 without external wait logic. Note that the ATA specification calls for all devices to be initialized in PIO mode 0 before possibly being configured for higher rates, including DMA.

The only reliable way I've found to efficiently implement ATA on fast processors is to use a CPLD or FPGA to control the timing. In it's simplest form it can assert a processor wait signal for register access and PIO modes plus take over the bus for the entire duration of a DMA block. DMA mode is most efficient in an FPGA using a dual-ported buffer between the two different clock domains and Ultra DMA adds a LOT of extra complexity.

I would suspect the reason that some [many?] CF cards work with non-compliant ATA interfaces is due to them not forcing the specification timings. I've definitely seen CF cards that will respond properly to PIO mode 4 timing even though they're configured for the much slower PIO mode 0. This may also explain why only certain brands of CF cards may work on a particular interface and also why physical disks might not. I've experienced hard drives that were picky about being properly configured with timing that matched the selected mode.
 
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