| Re: Question ISA BUS clock [message #6200 is a reply to message #6198] |
Mon, 01 April 2019 12:01   |
Sergey
Messages: 236
Registered: October 2015
Location: Portland, OR
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Senior Member |
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It would help to describe what are you trying to debug 
B30/OSC - 14.31818 MHz clock. In the original IBM PC, IBM XT, and clones of thereof this is the OSC output of 8284 clock generator.
B20/CLK - Buffered CPU clock, it is slightly delayed from the actual CPU CLK signal because of the buffer. In the original IBM PC/XT and the clones it is 4.77 MHz (exactly one third of OSC and aligned to it). In various "turbo XT" systems and early ATs this signal reflected the CPU clock frequency. In later/faster ATs (probably anything faster than 8 MHz), it is an ISA bus clock, that might not be correlated to the CPU clock.
AEN - Indicates a DMA bus cycle, used by I/O devices to prevent from being selected during the DMA cycles.
ALE - In 8088/8086/80188/80186/80286 it is activated during the second half of T1 bus cycle, while the CPU outputs the address. It is used by address latches to latch the address. It is not particularly useful (and even harmful) in PC/XT/8-bit ISA bus systems /cards. In AT/16-bit ISA variant higher address lines (LA17-LA23) are unlatched, and this signal can be used by the ISA controllers to determine when the address is stable and latch or decode it.
In your diagram above wide ALE pulses are rather weird. I'd expect to see only the short ones.
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