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Re: A simple CP/M Z80 SBC without glue logic [message #6130 is a reply to message #6126] Thu, 14 March 2019 10:50 Go to previous messageGo to previous message
wsm is currently offline  wsm
Messages: 232
Registered: February 2017
Location: AB, Canada
Senior Member
Interesting idea. This is similar to what I did when I started my Z180 MinZ design ... minimal components. I think there might be a COUPLE of additional chips required. Firstly, I like to always add a reset supervisor / voltage monitor which also allows a reset pushbutton. I admit to software development goofs that require resets Smile

Serial I/O can be handled on a header for external USB or RS-232 adapters. I chose to make two variants of my board, one with a CP2015 USB bridge and one that allows either an RS-232 translator or a TTL header.

At first glance it appears the KIO CS* can be tied low since it also uses IORQ* and is the only I/O device. However, I think that may get into some issues with interrupt responses (M1* plus IORQ*) which would be both a vector read AND an I/O write.

The other question I would have is on the ROM / RAM chip selects. There is a need to differentiate both memory cycles (MREQ*) and RAM vs. ROM. I know there are some memories with dual selects (can't remember exact ones offhand) but many [most?] of the newer ones only have a single select and expect an external decoder.

Perhaps weak pull-up vs. pull-down on a KIO port can differentiate ROM vs. RAM on reset and until the KIO can be programmed. That still leaves the issue of differentiating I/O versus memory cycles.

Just my $.02 while I wait for another cup of coffee to kick in. I'm thinking that you will require a decoder i.e. glue.

While you're toying with ideas, why not also look at the Z84C15 which has basically the same features of the Z80+KIO but integrates the CPU and also has memory selects. The downside is that it's a VQFP-100 package.
 
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