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| Re: Bus Buffers/Z80 Electrical Characteristic Questions [message #6671 is a reply to message #6662] |
Tue, 15 October 2019 07:37   |
jcoffman
Messages: 332
Registered: October 2015
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Senior Member |
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For bus buffers you cannot beat the 74LS244 and 74LS245. As receivers, they incorporate hysteresis on their inputs, important on a (possibly) noise-prone bus. But beware: the 74HC, 74HCT, 74ALS, 74F, 74S, 74AS logic families do NOT have these Schmitt trigger inputs.
If you have looked at schematics of the ECB SBC's and ECB peripherals, the CPU cards have 74LS drivers/receivers on the data lines, and the peripheral cards similarly have 74LS receivers/drivers on the data lines, and often, 74LS244 receivers on address lines. On some of the boards, the address line receivers are 74LS682/688 parts, the 74LS versions also having Schmitt trigger inputs.
The Retrobrew ECB bus, although not terminated, appears to be a particularly quiet, i.e., noise-free, bus.
--John
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| Re: Bus Buffers/Z80 Electrical Characteristic Questions [message #6674 is a reply to message #6665] |
Tue, 15 October 2019 10:41 |
protocall7
Messages: 20
Registered: October 2019
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Junior Member |
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just4fun wrote on Tue, 15 October 2019 02:20Hi, about the datasheet, here you can find all the info for both the NMOS and CMOS versions, including DC specs you are looking for...
Hi just4fun -- I feel like I'm missing something in the spec sheet you linked. I've been looking through the D.C. Characteristics and Absolute Maximum Ratings sections hoping to find Iin, but the only current ratings I'm seeing are the Icc currents for active/standby, as well as the input/tri-state leakage currents.
Am I just skimming over it and not seeing it, or perhaps did Zilog name the input current rating something I'm just not recognizing?
It does seem from jcoffman's comment that I might be on the right track with my design, regardless.
[Updated on: Tue, 15 October 2019 10:41] Report message to a moderator |
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| Re: Bus Buffers/Z80 Electrical Characteristic Questions [message #8464 is a reply to message #6676] |
Wed, 14 April 2021 10:55 |
lynchaj
Messages: 1079
Registered: June 2016
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Senior Member |
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Hi
Facing a similar design issue on the Z80 multi board computer, I opted for a fully buffered Z80 processor board. 74ls244s for address bus and MREQ IORQ RD and WR. 74ls245 for data bus. 74ls367 for inputs like CLK, BUSRQ, RESET, INT, NMI, and WAIT. The remaining four outputs caused me the most grief but went with a 74ls07 OC buffer with weak pull ups for HALT, BUSACK, M1, and RFSH. The theory being if there is another transmitter on the bus at least they won't get in the way.
Not sure that the last four are right but I haven't found anything else and the data sheet is silent on sharing those signals. Going OC buffer seemed like a good idea although I would have preferred to use a 74ls244 had been able to find a way to share and coexist on a common bus. Such as how to tri-state those output signals?
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| Re: Bus Buffers/Z80 Electrical Characteristic Questions [message #8469 is a reply to message #8468] |
Wed, 14 April 2021 17:45 |
lynchaj
Messages: 1079
Registered: June 2016
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Senior Member |
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Yeah, I don't think anyone can dispute the CMOS parts are much more modern and more capable than their older counterparts. CMOS Z80 beats NMOS Z80 in most respects. I also recall when CMOS parts came out they were super sensitive to ESD and required special handling or they got silently damaged and/or destroyed. I don't think that is as big an issue as it used to be. I like the 74ls parts the best as they are a good compromise of features. However some of the newer parts are just amazing in how little power they use and heat they produce. Just amazing.
I have an old homebrew S-100 system in my basement with a bunch of old low density boards. Practically a full rack of boards and when it runs it feels almost like a toaster there is so much heat rising off of it. Haven't booted that machine in quite a while because it practically dims the lights when it starts. Also it came with a UV eraser inside the chassis which was just bizarre. I removed the bulb for safe keeping.
[Updated on: Wed, 14 April 2021 17:49] Report message to a moderator |
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| Re: Bus Buffers/Z80 Electrical Characteristic Questions [message #8471 is a reply to message #8470] |
Thu, 15 April 2021 06:54 |
wsm
Messages: 226
Registered: February 2017
Location: AB, Canada
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Senior Member |
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I was never very impressed with Zilog's documentation ... most of the required information is there but in a jumbled way. For the Z180 I still primarily use the Hitachi HD64180 manual which is MUCH better and Zilog finally used it as the basis of their updated manuals. One handy feature of the Z180 manual is a very clear table of every pin's state during RESET, BUSACK and SLEEP.
Unless you're using DRAM, interfacing the Z80 is pretty basic so perhaps I'm missing the point of your question. Are you planning on a multiprocessor configuration? The HALT*, BUSACK*, M1* and RFSH* signals reflect states of the bus master and if using an MP with shared peripherals then there's already going to be extra signals for each processor from the arbiter. On a single processor system you can just buffer them onto the bus in case peripherals want to use them. The M1* timing is used for I/O versus interrupt acknowledge so it should have the same timing delay as IORQ* ... using OC will add very significant rise time delays.
One thing to watch out for is that the clock input Vihc is specified as Vcc-0.6V whereas all other pins are Vih minimum of 2.2V. On the Z180, RESET*, EXTAL and NMI* all require the higher Vih. In my opinion, the CLK signal is tightly tied to the processor speed and thus should be on the processor board and possibly distributed out to the bus rather than as a bus input. As to the question of a buffered reference design, I think that goes back to my previous point about fanouts and every design is going to have unique requirements.
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| Re: Bus Buffers/Z80 Electrical Characteristic Questions [message #8472 is a reply to message #8471] |
Thu, 15 April 2021 07:18 |
lynchaj
Messages: 1079
Registered: June 2016
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Senior Member |
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Not really planning for a multi-processor bus but would like to implement in such a way as to not preclude that possibility. It would be simple to just run HALT, BUSACK, M1, and RFSH through a 74ls244 or other buffer but on what conditions are they tri-stated? I could never find an answer in the datasheet so that essentially means only a single processor (or processor like device) on the bus with control of those signals. Using OC is sort of a compromise so that you can have multiple transmitters with the ability to pull those signals to low without bus contention. Not perfect but lacking an alternative.
Regarding the clock, my next revision of the processor board is going to have the option for an on-board oscillator or to use the clock signal on the bus. For the low speed (4 MHz or so) it should be OK on the bus while I work out the other design issues of going with a fully modular design. What forced this issue is over time the RTC circuit and CPU clock circuit kind of merged together in an unexpected way. It wasn't like that for the original SBC V1 design but evolved over time. So now its an issue by breaking into modules whereas before everything was integrated together in an SBC and it didn't matter.
The Z80 MBC is sort of an experiment since this issue of modularity has been nagging at the back of my mind since practically the start of the original SBC. Once those design decisions were in place it basically locked them in and it is difficult to make changes without completely breaking backward compatibility. I am hoping to use a different approach with Z80 MBC to allow for more flexibility. For instance, it would be nice to include a CTC or dual serial without a total redesign or the overhead of a full blown ECB backplane, etc. It is possible that the outcome of the experiment is that converting the SBC into a modular design is not feasible. In that case at least it answered my question.
That's why this question of Z80 bus buffers is so important and I am surprised it hasn't been more rigorously hashed out (as best I can find). The question forms the basis as to what constitutes a modular Z80 design. One of my goals is to have as few features on the processor board as possible. That's kind of budged a bit over the implementation as the current processor board now has a reset circuit and a wait state generator. The next iteration will include a local oscillator option as well. Still trying to keep that necessary feature set as small as possible so everything else can be a plug in (and thus changeable) module.
[Updated on: Thu, 15 April 2021 07:44] Report message to a moderator |
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| Re: Bus Buffers/Z80 Electrical Characteristic Questions [message #8473 is a reply to message #8472] |
Thu, 15 April 2021 08:26 |
wsm
Messages: 226
Registered: February 2017
Location: AB, Canada
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Senior Member |
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Perhaps your answer to tri-states for HALT, BUSACK, M1 and RFSH can indirectly be answered by looking at the Z180 which is better documented. All four of these signals are ALWAYS outputs with no tri-state. If you're trying to go the multiprocessor route you'll need an arbiter that determines which processor has control of the main bus. So the solution is pretty simple ... those four signals have their own tri-states controlled by the bus master select signal which also has an onboard pullup or pulldown for single processor use.
I've come full circle on the bus question as it eventually leads to all sorts of future issues such as interrupt and busreq daisy chaining. I've gone to single boards with what I perceive as all the required features and possibly with a limited expansion for an I/O bus, I2C or SPI. One of the main costs used to be PCBs but they're now cheap and easy to change with CAD. And yes I've also gone to the extreme with the NYOZ system allowing expansion boards with up to 16 slave Z180's at 33MHz plus all sorts of memory and I/O options. The BIOS became a real pain allowing for all the possible options.
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