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multicomp IIc AS6C1008 [solved] [message #3929]

Mon, 11 December 2017 05:59

b1ackmai1er
Messages: 396
Registered: November 2017

Senior Member

Good Evening,

I have a spare AS6C1008 sitting in my parts box at the moment and was wondering if the Multicomp IIc can be configured to use two of these i.e. 256K?

Thanks.

[Updated on: Sat, 23 December 2017 03:22]

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Re: multicomp IIc AS6C1008 [message #3930 is a reply to message #3929]

Mon, 11 December 2017 08:42

rhkoolstar
Messages: 276
Registered: October 2015

Senior Member

Yes, you can, You need to rewrite the VHDL code to get this working, as well as remap some of the pins.

I'm not sure if the CP/M implementation checks the amount of available RAM. Mine do not. (I only test for 512/1024 kB. Wink

so maybe you need to modify the BIOS code as well.

Rienk

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Re: multicomp IIc AS6C1008 [message #3933 is a reply to message #3929]

Mon, 11 December 2017 14:47

mscane
Messages: 111
Registered: October 2015

Senior Member

You could, providing the electrical connections to the chip are compatible.

You would need to change the way the /CS signals are generated in the VHDL code.

The MMU assumes a flat 1MB space in 16KB blocks but wolud work with a smaller address space.

I'm not sure what benefit the second chip would be though. The first chip would be sufficient for CP/M and CP/M 3.

The second chip would not be big enough for a usable RAM disk and depending on who's BIOS you are using, it probably would not be configured for the smaller ram disk.

Max

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Re: multicomp IIc AS6C1008 [message #3934 is a reply to message #3933]

Tue, 12 December 2017 06:37

rhkoolstar
Messages: 276
Registered: October 2015

Senior Member

A 192 kB RAM disk would be considered humongous in the CP/M era.
Rewriting a BIOS RAM disk size is not that hard. In most cases, changing the DPB (disk parameter block) should be enough.
there are many code examples on the WIKI.

Rienk

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Re: multicomp IIc AS6C1008 [message #3936 is a reply to message #3934]

Wed, 13 December 2017 01:39

b1ackmai1er
Messages: 396
Registered: November 2017

Senior Member

I think if I change this

n_externalRam1CS<= not(n_RomCS and n_internalRam1CS and not physicaladdr(19));
n_externalRam2CS<= not(n_RomCS and n_internalRam1CS and physicaladdr(19));

to this:

n_externalRam1CS<= not(n_RomCS and n_internalRam1CS and not physicaladdr(17));
n_externalRam2CS<= not(n_RomCS and n_internalRam1CS and physicaladdr(17));

the chip select will change from switching between 512k banks to switching between 128k banks.

I think I if I set the following jumpers:

A16 "2-3" -- connect PIN25_A16 to CHIP 1 A16 then both chips will be connect with A0..A16 so see the full 128k addressing.
A18 "2-3" -- connect PIN32_A18 to CHIP 1 A18 then both chips will be connected to A18 which is inconsequential since this pin is NC

The problem for me is how to set both pin 30's to high for the secondary chip enable.

A17 "1-2" will set CHIP 1 high but CHIP 2 will still be driven by PIN31_A17 which will probably be low. In hardware I could pull pin 30 out of the second chip and connect it to 3.3v.

I don't know how to set PIN31_A17 high permanently in code.

Any suggestions?

Also, how would I actually do a ram test on this?

Regards Phil

[Updated on: Wed, 13 December 2017 02:10]

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Re: multicomp IIc AS6C1008 [message #3937 is a reply to message #3936]

Wed, 13 December 2017 03:44

b1ackmai1er
Messages: 396
Registered: November 2017

Senior Member

Since this post I have been playing around with this:

n_externalRam1CS<= not(n_RomCS and n_internalRam1CS and not physicaladdr(17));
n_externalRam2CS<= not(n_RomCS and n_internalRam1CS and physicaladdr(17));
Jumper A16 "2-3"
Jumper A18 "2-3"
Jumper A17 "1-2"

And this boots and will load CP/M which is something. Both RAM #1 & #2 are reported ok but there is still just 1 RAM chip installed. But it runs.

I had an idea to overcome the Jumper A17 - PIN31_A17 inconsistency:

I have defined a new output in the CycloneIIc entity code

CHIPOE : out std_logic:='1';

Then I have disabled the sramAddress[17] in the pin Assignment editor and then added a new pin

CHIPOE Location PIN_31 Enabled = Yes

So now I think PIN_31 is always giving a high output so I reset Jumper A17 "2-3" so both chip pin 30 (second chip enable) are connect to a high input.

I have recompiled and the board still boots to CP/M with one chip so it might be working.

Any other ideas, better ways to do or see any flaws in this approach?

How could I test I have full 256K of contiguous ram?

Thanks.

(Edit: now realize this is what Rienk suggested regarding editing pins. Wink

[Updated on: Wed, 13 December 2017 04:47]

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Re: multicomp IIc AS6C1008 [message #3938 is a reply to message #3936]

Wed, 13 December 2017 03:56

rhkoolstar
Messages: 276
Registered: October 2015

Senior Member

You need to change
sramAddress : out std_logic_vector(18 downto 0);
to
sramAddress : out std_logic_vector(16 downto 0);

assign PIN_31 to something like sRamAltCS (was sramAddr[17] Wink

in the Pin Planner
(delete sramAddr[18] while you are at it Smile

and (in the "port" section)

sRamAltCS : out std_logic :='1'

I'm probably forgetting something, but this should get you somewhere

Rienk

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Re: multicomp IIc AS6C1008 [message #3939 is a reply to message #3937]

Wed, 13 December 2017 04:04

b1ackmai1er
Messages: 396
Registered: November 2017

Senior Member

More progress of sorts ...

I have plugged my second ram chip in and still boots ok to CP/M.

The only way I could think of testing was to try CP/M 3.

So I have imaged CP/M 3 onto the next partition.

It booted with the following output:

TT1 OK
CPU OK -- Cyclone II C SoC
RAM #1 OK
RAM #2 OK
SD Card OK

Boot load completed

Multicomp Loader 0.1

Extended Z80 Debug Monitor Version 0.8i by Max Scane September 2015

Booting CP/M 3

LDRBIOS3 V0.1 for the Multicomp SBC by Max Scane May 2014

CP/M V3.0 Loader
Copyright (C) 1982, Digital Research

BNKBIOS3 SPR E900 0E00
BNKBIOS3 SPR B500 0B00
RESBDOS3 SPR E300 0600
BNKBDOS3 SPR 8700 2E00

56K TPA

CP/M Version 3.0, for the Multicomp SBC (Banked)
MD Driver assigned to drive A:
System partition is : HSA
LD Driver assigned to drive C:
LD Driver assigned to drive D:
LD Driver assigned to drive E:
LD Driver assigned to drive F:
C>

So I don't know what that i really telling me and I am still unsure how I can test the memory.

Regards Phil

[Updated on: Wed, 13 December 2017 04:38]

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Re: multicomp IIc AS6C1008 [message #3940 is a reply to message #3939]

Wed, 13 December 2017 04:41

b1ackmai1er
Messages: 396
Registered: November 2017

Senior Member

MP/M-II booting ...

MP/M II V2.1 Loader
Copyright (C) 1981, Digital Research
Nmb of consoles = 3
Breakpoint RST # = 6
Memory Segment Table:
SYSTEM DAT FC00H 0100H
TMPD DAT FB00H 0100H
USERSYS STK FA00H 0100H
XIOSJMP TBL F900H 0100H
RESBDOS SPR ED00H 0C00H
XDOS SPR CB00H 2200H
BNKXIOS SPR C000H 0B00H
BNKBDOS SPR 9D00H 2300H
BNKXDOS SPR 9B00H 0200H
TMP SPR 9700H 0400H
LCKLSTS DAT 9400H 0300H
CONSOLE DAT 9100H 0300H
-------------------------
MP/M II Sys 9100H 6F00H Bank 0
Memseg Usr 0000H C000H Bank 1
Memseg Usr 0000H C000H Bank 2
Memseg Usr 0000H C000H Bank 3

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Re: multicomp IIc AS6C1008 [message #3941 is a reply to message #3940]

Wed, 13 December 2017 04:52

rhkoolstar
Messages: 276
Registered: October 2015

Senior Member

Sorry, I can't help you with Max's CP/M implementation, as I can't find the sourcecode anywhere.
If you have a RAM disk (drive A: ? Wink

you can try filling it up. it should report errors/corrupt after some 190 kBytes
if it only "takes" about 60 kBytes the second RAM chip is not in play (yet)
stat A: should tell you the size it is configured to

Rienk

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Re: multicomp IIc AS6C1008 [message #3942 is a reply to message #3941]

Wed, 13 December 2017 05:41

b1ackmai1er
Messages: 396
Registered: November 2017

Senior Member

Thank you but STAT is not available on the CPM3 disk.

From reading past threads I think CPM3 is preconfigured for a fixed memory size/banks and does not do a memory check to determine number of memory banks available.

Not even sure how to get the file size on CPM3 Smile

Sorry I missed your earlier post about the code changes.

Thanks.

[Updated on: Wed, 13 December 2017 05:46]

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Re: multicomp IIc AS6C1008 [message #3944 is a reply to message #3942]

Wed, 13 December 2017 11:02

rhkoolstar
Messages: 276
Registered: October 2015

Senior Member

CP/M 3 probably uses 128 kByte. So when a RAM disk is available it should accept some 128 kByte of data before something bad happens.

on CP/M 3 try SDIR A: or SHOW A:

Rienk

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Re: multicomp IIc AS6C1008 [message #3952 is a reply to message #3939]

Thu, 14 December 2017 00:55

mscane
Messages: 111
Registered: October 2015

Senior Member

CP/M 3 only uses 128 KB (banks 0, 1 and common) so it would be contained to the first chip.

The second chip would get used by the RAM disk on a:. However, since it is not the full 400Kb (approx) it is not a good test.

Try using the Bank command in the monitor.

Each bank is 48KB (0 - 0xdfff). The MMU splits the physical memory into blocks of 16 KB.

Therefore:

Bank 0 would contain physical blocks 0,1,2 with 3 set to common.
Bank 1 would contain physical blocks 4,5,6 with 3 set to common.
Bank 2 would contain physical blocks 7,8,9 etc...

Select a bank then do some reads/writes (use the sub command) to the banked area.

You should be able to workout which banks contain real ram.

Max

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Re: multicomp IIc AS6C1008 [message #3953 is a reply to message #3942]

Thu, 14 December 2017 00:59

mscane
Messages: 111
Registered: October 2015

Senior Member

Yes, that version of CP/M 3 assumes 512KB of ram.

A later version sizes the RAM and configures the disk information accordingly but only in increments of 512KB.

Max

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Re: multicomp IIc AS6C1008 [message #3961 is a reply to message #3952]

Fri, 15 December 2017 04:00

b1ackmai1er
Messages: 396
Registered: November 2017

Senior Member

Thanks Max,

Do you mean (0-0xC000) ?

Also do I need to avoid writing below 0x100 to avoid rom being switched in?

I gather that the rom is copied to ram block 3?

I hooked up the LED to the chip select outputs.

Selecting Bank 0 light chip select 1 LED only
Selecting Bank 1 light chip select 1 LED only
Selecting Bank 2 light chip select 1 LED only
Selecting Bank 3 light chip select 1 & 2 LED. Chip select 1 LED is brighter.
Selecting Bank 4 light chip select 1 & 2 LED. Chip select 1 LED is brighter.

I have copied:
00's to bank 0, 0x100-0xc000
11's to bank 1, 0x100-0xc000
22's to bank 2, 0x100-0xc000
33's to bank 3, 0x100-0xc000
44's to bank 4, 0x100-0xc000

and then gone back and checked that they are still there and not overwritten and it all looks ok.

So as far as I can see the chip select change is working and it is mapping the 256k correctly ???

Edit: 0-0x100 can be modified, I was getting I/O space for bank selection mixed up with address space.

[Updated on: Fri, 15 December 2017 21:57]

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Re: multicomp IIc AS6C1008 [message #3965 is a reply to message #3961]

Sat, 16 December 2017 08:15

b1ackmai1er
Messages: 396
Registered: November 2017

Senior Member

Hi Gents,

I have now hit the limitation with the monitor and cp/m code not supporting the 256Kb modified vhdl core.

To get this supported under CP/M et al, should I move to the MC-2G-1024 package as a new starting point and generate my own CP/M package?

Thanks Phil

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Re: multicomp IIc AS6C1008 [message #3968 is a reply to message #3965]

Sat, 16 December 2017 14:44

rhkoolstar
Messages: 276
Registered: October 2015

Senior Member

You could.

I posted that so people could change it to their liking. All the necessary sources are available and are commented (sort of)
If you have questions I'll happily answer them, but you have to make the changes yourself.

But you don't have to choose. You can try it and see if you like it. You may even make your own implementation.
This is what this hobby is all about.

Rienk

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Re: multicomp IIc AS6C1008 [message #3971 is a reply to message #3965]

Sun, 17 December 2017 16:59

mscane
Messages: 111
Registered: October 2015

Senior Member

The multicomp boards were designed to use 512KB RAM chips.

The version of CP/M you are using is hard coded to use one 512 KB chip for CP/M with the remainder for a RAM disk. In later versions I changed the geometry of the RAM disk so it could support one or two RAM chips (but for 512 KB chips only).

The problem with CP/M is that it requires a parameter block to describe each different disk format. You can either pre-define them or generate them at boot. Each method consumes RAM in the BIOS.

Max

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Re: multicomp IIc AS6C1008 [message #3973 is a reply to message #3971]

Mon, 18 December 2017 00:17

rhkoolstar
Messages: 276
Registered: October 2015

Senior Member

Quote:

Each method consumes RAM in the BIOS.

Not necessarily. In CP/M 2 or MP/M you can put all BIOS configuration code in the sector buffer and/or allocation vector space of the drives. This will be overwritten once the drives are accessed. In CP/M 3 you can write the initialization code in a banked memory segment.
This way, initialization is conducted at no cost to the TPA.

Phil can either write a memory sizing routine and change the RAM disk DPB on the fly or just hard code a 256kB version. (just change the DPB)
I suggest the second method, as a first start. Just to get it working.

Rienk

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Re: multicomp IIc AS6C1008 [message #3974 is a reply to message #3973]

Mon, 18 December 2017 13:47

b1ackmai1er
Messages: 396
Registered: November 2017

Senior Member

Good morning gents,

Thankyou.

I have not compiled a CP/M system before but I think I could work out the code to adjust the dpb based on memory size if there is enough space.

Is the source code still available for the ROM-MJS/CP/M package that is on the wiki? Is there any documentation on how to create the disk images?

Thank you.

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Re: multicomp IIc AS6C1008 [message #3977 is a reply to message #3974]

Tue, 19 December 2017 03:08

b1ackmai1er
Messages: 396
Registered: November 2017

Senior Member

Hi Rienk, in your INSTALL.TXT file in the MC-2G-1024 package

CBIOS215.HEX is now CBIOS217.HEX in the package.
"GFFFB" should be "RFFFB"

Thank Phil

install CP/M2.2 on volume nnn
=============================
- hit reset followed by space
- Locate the CPM22.HEX file and copy-paste the contents at the monitor prompt.
- Locate the CBIOS215.HEX file and copy-paste the contents at the monitor prompt.
- type Pnnn,E000 to write this on volume nnn.
- Type Innn to format the directory on volume nnn.
- Type Snnn to start CP/M 2.2.
- Hit the reset button on the FPGA board. (do NOT cycle power! Wink

- Locate the DOWNLOAD4.HEX file and copy-paste the contents at the monitor prompt.
- Type GFFFB to restart CP/M 2.2 via the backdoor.
- Type SAVE 3 DOWNLOAD.COM
- Locate the CPM22FilesPkg.txt file and copy-paste this at the CP/M prompt.

you now can use this installation to complete the others.

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Re: multicomp IIc AS6C1008 [message #3978 is a reply to message #3977]

Tue, 19 December 2017 03:21

rhkoolstar
Messages: 276
Registered: October 2015

Senior Member

Hi Phil,

Thanks for the update, I'll correct it soonest.

I trust I did not confuse you too much Razz

Rienk

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Re: multicomp IIc AS6C1008 [message #3979 is a reply to message #3978]

Tue, 19 December 2017 05:51

b1ackmai1er
Messages: 396
Registered: November 2017

Senior Member

Hi Rienk,

I feel like Alice in wonderland.

Things are starting to come together. You've documented so much which is fantastic, thank you.
I've been stuck for the last couple of hours trying to get the download.com to work in cp/m.

I think it is failing due to input buffer overrun. Is there some sort of flow control for the serial line that should be set?

It especiialy likes to get in an endless loop in zsid download

Thanks Phil

[Updated on: Tue, 19 December 2017 05:52]

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Re: multicomp IIc AS6C1008 [message #3980 is a reply to message #3979]

Tue, 19 December 2017 06:33

rhkoolstar
Messages: 276
Registered: October 2015

Senior Member

Hi Phil,

It needs RTS to work (CTS on your terminal). If your terminal software is configured with 'no handshake' or no 'hardware flow control' you will have problems.

Maybe first try the 'easy install' method (just copy the system18.img file to your SD card) to see if all is working correctly

Rienk

[Updated on: Tue, 19 December 2017 06:33]

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Re: multicomp IIc AS6C1008 [message #3981 is a reply to message #3979]

Tue, 19 December 2017 14:42

positron
Messages: 78
Registered: November 2015
Location: Buenos Aires, Argentina

Member

Hi Phil, if you use TeraTerm terminal emulation software, you can add inter-character and inter-line transmit delays. Edit the file TERATERM.INI and modify the default 0 values by trial and error. I had a similar problem when I used no hardware handshake and managed to transfer many large files with this trick.

Below is the Serial Port Parameter section of the TERATERM.INI file that you have to change (last two lines and other suitable values depending on your connection speed, etc. Wink

;	Serial port parameters
;	  Port number
ComPort=1
;	  Baud rate
BaudRate=9600
;	  Parity (even/odd/none)
Parity=none
;	  Data (7/8)
DataBit=8
;	  Stop (1/2)
StopBit=1
;	  Flow control (x/hard/none)
FlowCtrl=none
;	  Transmit delay per character (in msec)
DelayPerChar=0
;	  Transmit delay per line (in msec)
DelayPerLine=0

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Re: multicomp IIc AS6C1008 [message #3982 is a reply to message #3981]

Wed, 20 December 2017 02:33

rhkoolstar
Messages: 276
Registered: October 2015

Senior Member

I would select FlowCtrl=hard (I guess that doesn't work? Wink

I am of little help here. I use Linux minicom. Works like a charm.

A common mistake is to wire RTS-RTS and CTS-CTS which does not work. These wires should be crossed, just like Rx and Tx.

Rienk

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Re: multicomp IIc AS6C1008 [message #3983 is a reply to message #3982]

Wed, 20 December 2017 03:33

positron
Messages: 78
Registered: November 2015
Location: Buenos Aires, Argentina

Member

Hi Rienk, I agree with you if your setup has hardware handshake capabilities. The problem is that many cheap USB-Serial modules lack RTS or DTR pins (the 4 pin variety), so you have to configure the connection with no handshake and rely on transmit delays. Not the best but works until you buy a more decent module (the so called 6 pin model).

Cheers, JL.

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Re: multicomp IIc AS6C1008 [message #3984 is a reply to message #3983]

Wed, 20 December 2017 05:04

b1ackmai1er
Messages: 396
Registered: November 2017

Senior Member

Hi Guys,

I am using Putty. It seems to have settled down at the moment. I am pretty sure I have the flow control wires around the right way, it's a 6-pin model, so I will see how I go and if I have trouble again I will try TeraTerm.

I have had a look at the code. The CPM22.asm and cmon.asm code appear pretty independent of the ram banking. As long as there is 64Kb for the boot process to complete all is well.
It seems that the only code I need to change to get the ram disk working with 128Kb or 256Kb is to change the memory detection code and disk paramter setting code in the CBIOS217.asm file.

Regards Phil.

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Re: multicomp IIc AS6C1008 [message #3985 is a reply to message #3984]

Wed, 20 December 2017 06:03

rhkoolstar
Messages: 276
Registered: October 2015

Senior Member

When you check my builderpage you see the USB-serial converter I use. It is really cheap and has all handshake wires implemented.

Phil, you got that right. CP/M 2.2 wants only 64 kBytes, CP/M-3 wants 128 kBytes. the rest is used as a RAM disk.

You can start with deleting the memory detection and just change the disk parameter block.... baby steps Smile

When you want to run CP/M 3, you need to change "disk.asm" and re-assemble

Rienk

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Re: multicomp IIc AS6C1008 [message #3986 is a reply to message #3985]

Thu, 21 December 2017 04:50

b1ackmai1er
Messages: 396
Registered: November 2017

Senior Member

Hi Rienk,

I am having a bit of trouble understanding the default dpb for the 1024kb. Are you able to explain?
The number of reserved tracks is set to 8 (MOFF) and each track is 16Kb, so the reserved track is 8x16kb = 128kb.
I dont understand why we have 128Kb reserved instead of 64Kb

Thankyou.

Edit: Ahhhh, from your comments it looks like you have reserve 64Kb in case cpm 3 is being loaded. So cp/m gets 64kb for runtime, 896kb for ram disk, 65kb unused. cp/m 3 gets 64kb runtime, 64kb ramdisk and the rest for bank switched memory? So for my case for cpm I can just have 4 tracks reserves and allocate 512kb-64kb for ram disk?

[Updated on: Thu, 21 December 2017 05:25]

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Re: multicomp IIc AS6C1008 [message #3987 is a reply to message #3986]

Thu, 21 December 2017 05:12

rhkoolstar
Messages: 276
Registered: October 2015

Senior Member

Ah, I wanted to have the same RAM disk available to CP/M 2 and CP/M 3 variants.
CP/M 3 uses 128 kBytes system space.

Once initalized the RAM disk will stay unaffected when switched between these variants.
MP/M destroys the RAM disk

with 512 or 1024 kBytes to waste, 64 kBytes was a small price to pay.

In your case I would allocate all available space tough.

Rienk

[Updated on: Thu, 21 December 2017 05:23]

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Re: multicomp IIc AS6C1008 [message #3990 is a reply to message #3987]

Thu, 21 December 2017 22:28

b1ackmai1er
Messages: 396
Registered: November 2017

Senior Member

Very clever, thank you

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Re: multicomp IIc AS6C1008 [message #3991 is a reply to message #3990]

Thu, 21 December 2017 23:52

rhkoolstar
Messages: 276
Registered: October 2015

Senior Member

Off course you realize that the RAM disk is mostly useless anyway. You can simply mount an 8 Mb volume and use that volume with all CP/M versions. The SD card is clocked at 25 MHz. It is almost as fast as the RAM drive. It is simply something to do with all that unused memory. You probably noticed I even used the blocking routine for the RAM disk. This is to trim down on BIOS code and maximize the available TPA. That is the only memory that really counts.

Rienk

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Re: multicomp IIc AS6C1008 [message #3992 is a reply to message #3929]

Fri, 22 December 2017 06:23

b1ackmai1er
Messages: 396
Registered: November 2017

Senior Member

Yes you are right there is not a lot of merit in the ramdisk, and the whole project is more of a technical challenge for using the 128Kb ram chips which is all I have.

I am not aware of the significance of shared deblocking routines, I just thought that was normal? I only have limited experience with CP/M from my youth.

Looking at your CBIOS.ASM code I can see the dpb for your 896Kb ram disk default to 447 blocks, but if one ram chip then the ram disk is 384Kb and it sets the DSM to 192 blocks. Shouldn't this be 191 blocks?

Are we able to choose how many directory entries we want? i.e. can we have 256, 512, etc ? Is there anything special about 128?

Thank you.

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Re: multicomp IIc AS6C1008 [message #3993 is a reply to message #3992]

Fri, 22 December 2017 07:05

rhkoolstar
Messages: 276
Registered: October 2015

Senior Member

CP/M blocking-deblocking: CP/M uses 128 byte blocks to transfer data to and from the disk. SD cards use a 512 byte block. So the BIOS buffers 512 kBytes for disk access. I use the same routine to access the RAM disk. Which is detrimental to its performance. But it saves on BIOS code and leaves more TPA space (Useful memory), Currently 58 kByte.

Oops, yes it should be 191. Well spotted! Thanks.

You can select any number of directories up to 16 allocation blocks worth. Just use full allocation blocks and change AL0 and AL1 accordingly. One directory can reference 16 (or Cool

blocks. When you guess the average fill of a directory is 0.5, you need 2*disksize/(blocksize*16) directories. For a 192 kbyte disk with 1k allocation blocks that would be 2*192/(1*16)=24. So select 32 as a minimum. With 64 you can support an average fill of about 0.2 (more, but smaller files)

You hit the nail on the head there. The fun is in getting it to work. Weather something is useful or not has no significance whatsoever.

Rienk

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Re: multicomp IIc AS6C1008 [message #3994 is a reply to message #3993]

Fri, 22 December 2017 08:06

b1ackmai1er
Messages: 396
Registered: November 2017

Senior Member

Thanks for the info on the deblocking.

I am having a hell of a time getting the freshly assembled bios version to work.

I think the Buildit.txt file has to be updated for the last line change on the v217 CBIOS.HEX file ???

:10FFE000000000000000000000000000000088FE8B
| |
:10FFF000000000000000000000000000000088FE7B

Versus ...

:10FFE000000000000000000000000000000092FE81
| |
:10FFF000000000000000000000000000000092FE71

Regards Phil.

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Re: multicomp IIc AS6C1008 [message #3996 is a reply to message #3994]

Fri, 22 December 2017 10:04

rhkoolstar
Messages: 276
Registered: October 2015

Senior Member

hi Phil,

Buildit.txt is not wrong. What happens is the the "PopAndRun" location changed.
Your edit is right.

You can mail (or PM) me your .asm file, if you are up a wall. (uhhm, that would be 'against a wall' Wink

Rienk

[Updated on: Fri, 22 December 2017 12:09]

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Re: multicomp IIc AS6C1008 [message #3998 is a reply to message #3929]

Sat, 23 December 2017 03:20

b1ackmai1er
Messages: 396
Registered: November 2017

Senior Member

Hi Rienk,

All sorted thanks!

A>dir m:
M: Ram$Disk
A>stat m:

Bytes Remaining On M: 188k

A>

https:// www.retrobrewcomputers.org/doku.php?id=playground:b1ackmai1e r:start

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Re: multicomp IIc AS6C1008 [message #3999 is a reply to message #3998]

Sat, 23 December 2017 03:26

rhkoolstar
Messages: 276
Registered: October 2015

Senior Member

congrats

Glad I could be of help

Rienk

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