| Re: Has anyone reverse engineered SP0256A external serial speech ROM [message #10767 is a reply to message #10766] |
Thu, 16 May 2024 07:57   |
plasmo
Messages: 916
Registered: March 2017
Location: New Mexico, USA
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Senior Member |
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Moving forward, I grounded the 5 high order addresses of W27C512 to convert it into a 2KB ROM and wired all addresses, data, and control of the 2KB ROM to CPLD. This way CPLD has complete control over the ROM.
The translation of serial ROM protocol of SP0256's C1, C2, C3, SerIn, SerOut, ROMCLK, and ROMDisable to parallel ROM are done inside the CPLD, specifically the ROMCntrl block.
The C1, C2, C3 signals are decoded at the rising edge of ROMCLK into ASRLD, PCLD, DSRLD, and DSRSH commands. The other 2 commands, STACKLD and RETURN are not decoded because I don't think they are in use. ASRLD command causes 16-bit shift register to be loaded with addresses; PCLD command causes lower 12-bit of the 16-bit shift register to be loaded into a 12-bit counter; DSRLD generates ROM chip select and load contents of ROM into a parallel-to-serial register and then post increment the counter; DSRSH command shift the parallel-to-serial register out of SerIn output pin.
I have not tested the above circuit in the prototype board, but did a test compilation to know the macrocell utilization is 60 macrocells which will fit in a small 64-macrocell CPLD in PLCC44 package. With the current CPLD, I have resources to read the contents of 12-bit counter, parallel-serial register, and various commands for debugging purpose.
Bill
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