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Home brew Linux SBC Project
The goal of this project is to produce a completely free (as in speech), open hardware home brew Single Board Computer (SBC) capable of running the Linux kernel & userspace applications. The design uses an 80486 CPU and an integrated main board chipset to implement the PC/AT support functions & memory controller in a single package. All design information is and will be publicly posted including EDA files, schematics, PCB layout drawings, firmware (including ROM BIOS), software, and anything else needed for anyone to replicate these boards. The design uses commercially available off-the-shelf components with no proprietary or hidden anything. If you notice any missing design information please notify me immediately on the RBC forums or private message.
This project draws on home brew computer builder experience from multiple prior boards
Development will be split into three phases:
- Phase 1: A full length ISA card form factor SBC with 486 CPU, OPTi 82C465MVB+82C602A PC/AT chipset+PC97338 SuperIO, and up to 64MB of DRAM.
- Primary goal - boot 486 CPU with custom test ROM (jump loop aka “jploop”).
- Secondary goal is to run serial port test (continuously dump characters to serial port output, aka “scream”).
- Tertiary goal is ring out remaining hardware subsystems and prepare list of fixes for future iterations of Phase 1 board in preparation for Phase 2.
- Phase 2: An integrated SBC motherboard with VGA, Ethernet, sound, etc. onboard & 3 ISA expansion slots.
- Sergey's ISA SVGA http://www.malinov.com/Home/sergeys-projects/isa-supervga
- Sergey's ISA OPL2 http://www.malinov.com/Home/sergeys-projects/isa-opl2-card
- Gryphon's ISA Ethernet https://www.retrobrewcomputers.org/doku.php?id=boards:sbc:gryphon_68030:start
- Possibly a port 80 POST display (if there is room) http://www.malinov.com/Home/sergeys-projects/isa-post-card
- Phase 3: 486 CPU, integrated PC/AT chipset+SuperIO+FPGA controller & DDR SDRAM controller, and support for 1GB of DDR SDRAM.
- Primary goal of Phase 3 - testing of the DDR SDRAM controller.
Phase 1 'Derpy'
Linux-SBC home brew 486 is an Open Hardware project. All the KiCAD EDA files are posted on the GitLab page and/or the RBC forum
As more open source files and software become available, they will be posted on this wiki and on the Gitlab page
All software is intended to be open source including ROM BIOS and Linux kernel & related operating system
Looking for people to review the Derpy schematic. See announcement on vintage-computers.com
Derpy 1.3 schematic PDF file in the files section below
Phase 2 (Name TBD)
Phase 3 (Name TBD)
source the 82C465MV/A/B, 82C602A, and PC87338VLJ/PC97338VLJ chips
- Looks to be very promising for parts availability. Claims to have chips we need in stock for reasonable price.
- I think the 82C465MVBs are out there. Here is a quick google search
- Maybe not the usual places but they are out there. It is a matter of finding a good supplier
- Octopart.com and UTSOURCE.NET also both claim to have 82C465MVB
- www.cpluselectronics.com 82C465MVB $26 each
- www.circleworld-ic.com 82C465MVB $13.60 each
- www.cyf-ic.com 82C465MVB $17.38 each
- www.ys-elec.com 82C465MVB $19.50 each
- www.angrandic.com 82C465MVB $17.00 each
- utsource.net 82C465MVB $30.31 each
- www.iconix-inc.com 82C465MV $16.79 each
- would you get some RFQs and try to identify a parts supplier? I'll bet there are others out there we can find with some Google and/or eBay searches
Regarding a starting point for CPUs during build and test phase, I recommend either the 16 MHz i486SX or the original 20 MHz i486DX.
- Why so low? Well even with a 4 layer PCB and lots of filter caps, etc. performance will vary with CPU clock speed. I think gearing initial build and test to the lowest speed setting will minimize the transmission line effects (microwave circuitry). Typically circuits behave as you'd expect below 25 MHz regarding trace length and impedance. Above 25 MHz, the transmission line effects start to take over and things get weird in a hurry.
- Assuming we can get the board working with the lower speed CPUs, it should be a straight forward scaling up the clock speed with faster CPUs to find the upper limits and/or where areas with problems.
- Both chips are 5V only and no clock doubling/tripling/etc. which are huge simplifying assumptions. The design supports faster clock speeds and clock multipliers but I don't recommend using them until the basic functionality is rung out.
What about a System ROM BIOS? My plan is to use coreboot SeaBIOS
- It will require some customization to address the 82C465MVB initialization and probably the PC97338 as well
Initial Built and Test Team for Derpy PCB