Table of Contents
ZoRC, Z80+oscillator+RAM+CPLD (Exploratory)
Introduction
This is a hand-wired design derived from ZRCC where the design is further simplified by eliminate the compact flash disk and upgrade the RAM to 512K so the CP/M file system can be stored in RAMdisk. There was a discussion about it (ZoRC) in google retro-comp group as well as in Hackaday
Features
- Z80 overclocked to 22MHz
- 512K RAM, 16 banks of 32K
- EPM7064S CPLD
- 22MHz oscillator
Theory of Operation
The original intent of this design is a very simple CP/M-capable Z80 computer that can be build by hand without pc board. This is possible because the pin assignment of CPLD is very flexible and RAM addresses & data can be re-assigned to facilitate point-to-point connection. By flipping the Z80 DIP on its back and shifting the RAM one pin up, 18 pairs of pins can be connected directly from Z80 to RAM. This arrangement reduces the number of manual connections by about 30%. The remaining connections can be made easier by assigning CPLD's pins such that they are close to the destination pins.
Altera EPM7064S is the key component for turning Z80 and RAM into an usable computer. The flexible combinatorial logic fabric of CPLD can be turned into a small ROM, 32 bytes in this case. This 32-byte ROM resides in location 0x0-0x1F when powered up. Beside the small ROM code, the CPLD also contains a simple serial receiver hardwired to 115200 N-8-1. The serial transmit is a simple register to be bit-banged by software. In the CPLD is also a 4-bit bank select register so the 512K RAM is partitioned into 16 banks of 32K per bank. The top 32K of Z80 memory space always maps to the top 32K of RAM; the bottom 32K of Z80 memory space is assigned one of the 15 banks depending on the bank select registers. Finally, there is a “magic” I/O location that Z80 can write to cause the 32-byte ROM to disappear from memory. This is important because CP/M expects lower memory space of Z80 to be all RAM.
After negation of reset, Z80 starts program execution in CPLD ROM. Z80 polls the CPLD serial receiver for incoming data. If no incoming serial data is detected after about 7 seconds, Z80 will jump to memory location 0xB000; if incoming data is detected, Z80 will discard the first character, and store next 256 bytes of serial data in RAM locations 0xB000 to 0xB0FF and then jump into location 0xB000. Normally, this 256-byte serial data is a program loader that loads and runs more sophisticated applications, such as CP/M BIOS/BDOS/CCP.
