Tiny68K Altera 7128SQC100 schematic
6/16/2017, Design that loads 32k bytes of serial EEPROM. Simplify the serial EEPROM commands (Dummy_Write, Sequential_Read) so they use fewer logic elements.
This is a basic 68000 single board computer with one unusual feature. The boot ROM is stored in an low-cost 256kbit serial EEPROM, 24C256. At power up or when reset button is pressed, the content of the serial EEPROM is copied into the low address of DRAM while 68000 is held in reset. When the copying operation is completed, the 68000 nRESET is released and it boots from the code in EEPROM. The design motivation is cost saving because serial EEPROM is significantly cheaper than two ROM devices; 16 meg DRAM is cheaper than the equivalent SRAM and the programmable logic required to load serial EEPROM and interface to DRAM is a low-cost, medium complexity CPLD which is needed in any case for a traditional design. Because the serial EEPROM is a small 8-pin device and the 16-meg DRAM is in space-saving 72-pin SIMM format, the resulting circuit board is smaller, thus at lower cost, . The theory of operation is described in greater details below.
The CPLD is an Altera EPM7128SQC100 that contains both the serial EEPROM loader as well as the DRAM controller. To copy the content of the serial EEPROM to DRAM, there are a number of distinct operations:
1. The serial EEPROM's internal address counter needs to be initialized to zero. This is done with a “Dummy Write” command where a 3-byte command consists of START-EEPROM Address-Low address-High address is sent serially to the EEPROM.
2. After the serial EEPROM's address counter is initialized to zero, a “Sequential Read” command is issued followed by continuous byte reads of the EEPROM. The serial EEPROM's internal address counter will automatically increment to next address for every byte read.
3. The serial EEPROM loader state machine is a large counter chain consists of a 15-bit byte counter for 32K bytes of data, a bit counters for 8-bit data plus 1-bit acknowledge, and a clock divider to divide down the internal 8MHz master clock to 500KHz serial clock. The 15-bit byte counter also serves as the address generator for the DRAM address such that the 3 most significant bits are presented during the RAS cycle and the 11 lower bits are presented during the CAS cycle. The least significant bit of the 15-bit byte counter determines the Odd/Even bytes, so it is not used for DRAM addressing.
4. Because 68000's data bus is 16-bit wide, the 72-pin SIMM DRAM is wired as a 16-bit wide device with the high 16-bit data bus connected to the low 16-bit data bus. The serial data from the EEPROM is shifted into a 16-bit data register. During the acknowledge cycle of the serial EEPROM read operation, the 16-bit data in the shift register along with 14 bit of address from the 15-bit byte counter (the least significant 15th address bit is the Odd/Even byte of a 16-bit word and not used) are used to drive the DRAM controller and write data into DRAM.
5. The serial clock rate is 500KHz or 2uS per bit and there are 9 bit per byte (8 data bit plus acknowledge), so it takes close to 600mS to copy the content of the 256k-bit flash into DRAM. Therefore the DRAM refresh logic must be operating during the copying operation. The refresh operation is CAS-before-RAS and runs in the background once every 128 master clocks (one refresh per 16uS).
6. At the end of the copying operation, the content of the serial EEPROM will reside in the lowest 32K bytes of DRAM. The base address of DRAM is at 0x0 so upon the negation of 68000 nRESET at the end of the copying operation, the 68000 will fetch valid data in DRAM just copied from the serial EEPROM.
The software development environment for the serial EEPROM is as followed:
* EASy68K is the 68000 assembler which generates S-Record as its output.
* EASyBIN converts the S-Record to binary format
* a USB-based serial EEPROM programmer, CH341A, reads in the binary data and programs a serial EEPROM. This serial EEPROM becomes the boot device