Tiny68K construction log
The purpose of the first build is to develop the CPLD code, specifically the serial EEPROM loader. I have a rough idea of how the serial loader should work, but there are no detailed designs. I do not have a good simulator for the CPLD code, so I'm checking out the CPLD design using the actual hardware. The process of compilation and download of CPLD code is quite fast, so CPLD code checkout with the actual hardware is a viable approach. The board is a minimal build without most of the normal components.
This is embarrassing!
I received the replacement Altera USB Blaster last week. It works just fine so I'm ready to assemble the rest of the board, so I thought. Imaging my surprise when I realized DIP64 68000 is NOT 600mil wide! Instead it is 900mil wide. After a bit of denial and cursing I decided I can just solder one row, tilt the 900mil 68000 45 degree and connect the other row via wires. I don't suppose anyone would be interested in this version of the pc board now.
The good news is that I used the time waiting for USB Blaster to learn about Altera Quartus' native simulator. It is actually pretty decent and more than adequate for CPLD designs of modest complexity. I'm able to check out most of the serial EEPROM loader functionalities. It appears to be working–I'm able to load a small NOP loop code in serial EEPROM into DRAM, release reset and have 68000 execute it endlessly. A simple memory diagnostic checking part of the 16meg DRAM also works fine.
Between the DRAM controller, serial EEPROM loader, and address decoder I used up 95% of the logics in EPM7128–121 flip flops out of 128 available.
I program the 24C256 use a $5 USB CH341A serial EEPROM programmer. The toolchain for developing serial EEPROM bootcode in 68000 assembly is:
write & assemble code in EASy68K–>convert S Record to binary file with EASyBIN–>load the binary file with CH341A.exe and program the AT24C256 serial EEPROM.
EASy68K & EASyBIN are downloaded from easy68k.com
CH341A can be found from the download link of this youtube instruction on how to use EEPROM programmer:
All 68000's 16 megabyte memory space is taken up with a 16meg SIMM module except the top 32K bytes which are allocated to 68681 (DUART), IDE, and the expansion edge connector. The DRAM should be fast enough to run at zero wait for the fastest 68000 (20MHz). I have a 68HC000P10 running at 8Mhz right now. The refresh logic is CAS-before-RAS running automatically invisible to the the 68000 by inserting wait state to DRAM access during a refresh cycle. The monitor is about 11K bytes. The serial EEPROM loader loads half (16K bytes) of the AT24C256 into low memory of DRAM at powerup or reset. The serial clock is 500KHz so it takes about 300mS to load the monitor, barely noticeable.
The monitor uses EASy68k trap #15 services for I/O so Lee Davison's EhBasic runs with very little modifications– two changes: org to 0x4000 & disable DUART interrupts. I got the ASCII art program from tobster's hackaday page and I use it as a performance benchmark. The program takes 102 seconds to run on the 8MHz Tiny68k. It takes 29 seconds on Tiny030, 22MHz 68030.
I built up the board mostly with my existing inventory of parts, but since low cost is the main goal of this project, I look around eBay for 10pcs lot (shipping excluded) to find out how close it comes the $10 goal:
16meg SIMM72, $4
SIMM72 socket, $1.5
Altera EPM7128SQC100-15, $3
pc board, $0.5
So that's $15.4 for major parts and probably $2 for miscellaneous parts. Definitely over $10, but it is about $10 if you already have spare 68000, 16 mega SIMM, and miscellaneous parts,
The board is populated with a 44 pin IDE connector with a 256meg compactflash inserted